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Lect 4: Instruction Encoding and Instruction Set

Lect 4: Instruction Encoding and Instruction Set. T T T T T T T T. T T T T T T T T. mod TTT r/m. 7. 7. 0. 0. d32| 16 | 8 | none. data32 |16 |8 | none. 76 5 3 2 0. 7 6 5 3 2 0. ss index base. “mode r/m” byte. “s-i-b” byte. address displacement. immediate data.

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Lect 4: Instruction Encoding and Instruction Set

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  1. Lect 4: Instruction Encoding and Instruction Set

  2. T T T T T T T T T T T T T T T T mod TTT r/m 7 7 0 0 d32| 16 | 8 | none data32 |16 |8 | none 76 5 3 2 0 7 6 5 3 2 0 ss index base “mode r/m” byte “s-i-b” byte address displacement immediate data opcode (one or two bytes) (T represents an opcode bit.) register and address mode specifier Instruction Encoding General Instruction Format

  3. Encoding of Operand Length Field w Field Operation Size Operation Size During 16-bit During 16-bit Data Operations Data Operations 0 8 Bits 8 Bits 1 16 Bits 16 Bits Encoding of reg Field When w Field is not present in Instruction

  4. Encoding of 16-bit Address Mode with “mod r/m” Byte

  5. Encoding of 32-bit Address Mode with “mod r/m” Byte (no ‘s-i-b’)

  6. Encoding of 32-bit Address Mode( “mod r/m” byte and “s-i-b” byte present): * Important Note: When index field is 100, indicating no index register, then ss field MUST equal 00. If index is 100 and ss does not equal 00, the effective address is undefined.

  7. Encoding the instruction in Machine code • Example: • MOV BL, AL ; MOV opcode byte: 100010dw • d = 0 REG field is source; w =1 for word operation; mod r/m = 11 011; REG = 000 • First byte : 10001000 (88H); Second byte: 11 000 011 (C3H) • ADD [BX][DI]+1234H, AX; ADD opcode byte : 000000dw • d=0 REG field is source; w =1 for word operation; mod r/m = 10 001; REG = 000 • First byte : 00000001 (01H); Second byte: 10 000 001 (81H) • Resulting Machine code: 01813412H

  8. Encoding the instruction in Machine code • MOV ECX,2 ; MOV opcode byte: 1011w reg (immediate to reg short form) MOV AX,[EBX+2*ECX] MOV opcode byte: 1000101w (reg/mem to reg) • MOV ECX,2 ; 1011 1 001 (B9H) 0000 0010 0000 0000 0000 0000 0000 0000 • MOV AX, [EBX+2*ECX] • First byte : 10001011 Second Byte: 00 000 100 Third byte: 01 001 011 mod REG r/m ss index base • The Resulting Machine code: 8B044B • Address size prefix : 01100111 (67) ; Operand size prefix: 01100110 (66) • The Result: 66 | B9 00000002 67 | 8B 04 4B

  9. 80386 Instruction Set • 80386 base instruction set encoding table: See Fig 4.5 • Instruction Types • General Data Transfer • Arithmetic/Logic • Shift/Rotate • Bit test and bit scan • Flag Control • Control Transfer • String handling • System Control

  10. General Data Transfer • Data Transfer Instructions • MOV : 8 instructions ; operation: (dest) ¬ (src), Flags Affected: none • MOV AX,[BP] 10001011 01 000 110 0000 0000 mod reg r/m displacement • There are several machine codes to represent one MOV instruction. The assembler must choose an efficient one. • MOVSX: sign-extend MOVSX EBX, AX (reg from reg/mem) • MOVZX: zero-extend MOVZX CX, DATA (reg from reg/mem)

  11. General Data Transfer • XCHG operation (dest) « (src) ; flags affected : none • reg/mem with reg, reg with accumulator (short form) • XCHG AX,DX • XLAT : Translate String ; operation (AL) ¬ ((AL)+(BX)) ; flags affected: none • Load Effective Address and Load Pointer Instructions • LEA : Load effective address ; LEA SI, [DI+BX+5H] • LDS, LSS, LES, LFS, LGS : Load full pointer (offset: SBA) into reg and seg reg • PUSH operation : ((SP)) ¬ (src) (SP) ¬ (SP)-2 flags affected: none • POP • PUSHA, POPA (all general registers onto/from stack) • PUSHF, POPF

  12. Arithmetic Instructions • Arithmetic Instructions • ADD, ADC, INC, AAA, DAA • SUB, SBB, DEC, NEG, AAS, DAS • MUL, IMUL, AAM, DIV, IDIV, AAD, CBW, CWD • AAA : ASCII adjust for addition; flags affected: AF, CF, OF, SF, ZF, PF undefined • operation: ALcarry ¬ (AL) >0F9H; if ((AL)&0FH) >9 or (AF) = 1 then (AL)¬((AL)+6)&0FH; (AH)¬ (AH)+1+ALcarry; (AF) ¬ 1; (CF) ¬1; else AF¬ 0; CF¬ 0; (AL) ¬(AL)&0FH ;

  13. Arithmetic Instructions • Example : AL : 32H ASCII code for number 2; BL: 34H ASCII code for 4 ADD AL,BL ---- AL :66H AAA ----- AL : 6H • DAA (Decimal adjust for addition: two packed decimal) • operation: if ((AL)&0FH)>9 or (AF)=1 then (AL) ¬(AL)+6, (AF) ¬ 1 if ((AL)&0F0H) >90H or (CF) =1 then (AL) ¬ (AL)+60H, (CF) ¬ 1

  14. Logic Instructions • Logic Instructions • AND, OR, XOR, NOT • Shift Instructions • SAL/SHL, SHR/SAR, SHLD, SHRD: • SHL AX, 1; SAR AX, CL • Rotate Instructions • ROL, ROR, RCL, RCR • ROR AX,1; ROL AX, CL

  15. Bit Test Instructions • Bit Test and Bit Scan Instructions • BT(Bit Test), BTR(Bit test and reset), BTS(Bit test and set), BTC(Bit test and complement), BSF(Bit scan forward), BSR(Bit scan reverse) • BT D, S ; CF ¬ BIT[D,S]; saves the value of the bit indicated by the first operand and the bit offset into the CF flag • BSF r16,r/m16 or BSF r32, r/m32 ; scans the bits in the second word or double word operand starting with bit 0. The ZF flag is set if all the bits are 0; otherwise, the ZF flag is cleared and the destination register is loaded with the bit index of the first set bit.

  16. Flag Control Set • Flag-Control Instructions • LAHF(Load AH from flags), SAHF(Store AH into flags), CLC, STC, CMC, CLI, STI • AH : |SF|ZF| - |AF| - |PF| - |CF| • Compare and Set Instructions • CMP • SETcc r/m8: if condition then r/m8 ¬ 1(not FF) else r/m8 ¬ 0; • SETA, SETAE,.....

  17. Control Transfer • Jump Instructions • Unconditional(JMP) and Conditional Jumps(JA, JAE, .... ) • JMP : Intrasegment jump, Intersegment jump • Intrasegment jump : short(8-bit displacement: -126 to +129), direct within segment (16-bit or 32-bit relative), r/m indirect with segment • Intersegment jump : direct intersegment (full offset and selector), indirect intersegment • Jcc : conditional jump; 8-bit or full displacement • JA, JAE, ....

  18. Control Transfer • Subroutines and Subroutine-Handling Instructions • CALL and Return Instructions • CALL : intrasegment and intersegment call; • Intrasegment : CALL rel16, or rel32, CALL indirect within segment • Intersegment : CALL direct intersegment, CALL indirect intersegment • RET • Intrasegment : RET within segment, RET within segment Adding Immediate to SP • Intersegment : RET, RET adding immediate to SP

  19. Control Transfer • Stack Frame Instructions: ENTER and LEAVE • to allocate and deallocate a data area called a stack frame • ENTER : make a stack frame • ENTER imm16,0; Make procedure stack frame • ENTER imm16,1; Make stack frame for procedure parameter • ENTER imm16,imm8: Make stack frame for procedure parameter • first operand : the number of bytes to be allocated on the stack for local data storage second operand: lexical nesting level of the routine

  20. Procedure A Procedure B Procedure C Enter 32, 1 Enter 12, 2 Enter 16, 3 Leave Ret Leave Ret Leave Ret Control Transfer Data for Proc. C (16 bytes) BP for Proc. C BP for Proc. B BP for Proc. A BP for Proc. B Ret addr for proc. B Data for Proc. B (12 bytes) BP for Proc. B BP for Proc. A BP for Proc. A Ret addr for proc. A Data for Proc. A (32 bytes) BP for Proc. A Old BP Stack frame for C BP when executing Procedure C Stack frame for B BP when executing Procedure B Stack frame for A BP when executing Procedure A

  21. String Handling • Loop and Loop-handling Instructions • LOOP, LOOPE/Z, LOOPNE/NZ: CX must be preloaded with a count • String and String-Handling Instructions • MOVSB/W/D, compare string, scan string, load string, store string • the contents of both SI and DI are automatically incremented or decremented. • REP : repeat string; • Check Array Index Against Bounds • BOUND r16, m16&16 : check if r16 is within bounds • BOUND r32, m32&m32: check if r32 is within bounds operation: if (LeftSRC < [RightSRC] or LeftSRC> [RightSRC+OperandSize/8]) then Interrupt 5;

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