A 14-bit, 200 MS/s digital-to-analog converter without trimming

1. A 14-bit, 200 MS/s digital-to-analog converter without trimming Kuo-Hsing Cheng; Tsung-Shen Chen; Chia Ming Tu;Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on Volume 1, 23-26 May 2004 Page(s):I-353 - I-358 Vol.1 指導教授：林志明 老師 研究生：黃信嵐 學號：95662008 2006.10.23

2. OUTLINE • ABSTRACT • INTRODUCTION • DAC SPECIFICATION PARAMETER • ANALYSIS OF DAC DESIGN • DAC ARCHITECTURE • SIMULATION AND COMPARE RESULT • CONCLUSION • Q&A

3. ABSTRACT • a 14-bit, low DNL, INL error, 200M sample/s, current-steering DAC without trimming. • A novel feedback gain stage current mirror. • the DNL and INL are lower than ± 0.5 LSB.

4. INTRODUCTION • The paper is partitioned the DAC into a segmented coarse sub-DAC and a R-2R ladder fine sub-DAC. • Segmented current-steering array has guaranteed monotonic characteristic. • resolution is relatively independent of integral linearity.

5. INTRODUCTION • A novel Negative feedback gain stages current mirror is used. • The DAC has good performance without laser trimming, to reduce the process mismatch.

6. DAC SPECIFICATION PARAMETER • Resolution • Integral nonlinearity error • Differential nonlinearity error • Settling time • Monotonicity

7. ANALYSIS OF DAC DESIGN • High Accurate Current Mirror Design

8. ANALYSIS OF DAC DESIGN • The output impedance of the node Vo by the following equation • The current mirror matching accuracy

9. DAC ARCHITECTURE • The partition DAC

10. An efficient approach in segmented DAC B11 B10 B09 B12 B13 B14

11. The current cells of segment DAC spared two parts

12. The R-2R ladder DAC

13. SIMULATION AND COMPARE RESULT • The 14-bit DAC layout view • total area is 1.6*1.4 mm^2. • TSMC 0.25um • 1P5M CMOS process. • 2.5V supply voltage. • output load resistor is 50 ohm.

14. The simulation at 200M sample/s • INL

15. The simulation at 200M sample/s • DNL

16. The DAC step response

17. The comparison result of various DAC design

18. CONCLUSION • novel feedback gain stage current mirror improves the DAC’s DNL and INL characteristic. • even considers Vt and β parameters mismatch, the DNL and INL are better than ±0.08 LSB and ± 0.18 LSB, respectively. • lower DNL error, lower INL error, higher operation speed, high resolution, and lower areaandpower dissipation.

19. REFERENCES • [1] K. H. Cheng, C. C. Chen, and P. Y. Li, “A high accurate and high output impedance current mirror,”in Proc. WSEAS Conf.CSCC, 2002, pp. 41-43. • [2] B. Razavi, Principles of Data Conversion System Design.New York: IEEE Press, 1995. D. A. Johns and K. Martin, Analog Integrated Circuit Design. New York: John Wiley & Sons, 1996. • [3] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design. 2nd Ed. New York: Oxford, 2002. • [4]L. Wang, Y. Fukastu, and K. Watanabe, “Characterization of current-mode CMOS R-2R ladder digital-to-analog converters,”IEEE Trans. Instrumentation and Measurement, vol.50, pp.1781-1786, Dec. 2001. • [5]A. R. Bugeja and B. S. Song, “A self-trimming 14-b 100-MS/s CMOS DAC,”IEEE J. Solid-State Circuits, vol. 35, pp.1841-1852, Dec. 2000. • [6]J. Hyde, T. Humes, C. Diorio, M. Thomas, and M. Figueroa,“A floating-gate trimmed, 14-bit, 250 Ms/s digital-to-analog converter in standard 0.25/spl mu/m CMOS,”in Proc. IEEE Int. Symp. VLSI Circuits, 2002, pp. 328-331. • [7] Tiilikainen, M.P.; “ A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC “ ,Solid-State Circuits, IEEE Journal of , Volume: 36 Issue: 7 , Jul 2001 Page(s): 1144 –1147 • [8] G. A. M. Van Der Plas, J. Vandenbussche, W. Sansen, M. S. J. Steyaert, and G. G. E. Gielen, “A 14-bit intrinsic accuracy Q2 random walk CMOS DAC,” IEEE J. Solid-State Circuits, vol. 34,pp. 1708-1718, Dec. 1999.

20. Q&A