GRPlacer : Improving Routability and Wire-Length of Global Routing with Circuit Replacement

1. GRPlacer: Improving Routability and Wire-Length ofGlobal Routing with Circuit Replacement Ke-RenDai,Chien-Hung Lu,Yih-Lang Li ICCAD 2009

2. Outline • Introduction • Preliminaries • Problem Formulation • Algorithm • Experiment Results • Conclusion

3. Introduction • Traditionally, placement and routing are performed sequentially and independently. • IPR [2] reinforces total wirelength and congestion information by performing global routing during placement to improve the total wirelengthand routability of placement.

4. Introduction • White Space Allocation (WSA) [3] involves allocating white spaces into a congestion region to reduce congestion. • RUDY [4] estimatesrouting demand based on rectangular uniform wire density. • [5] proposed a net overlapping removal technique to lower congestion in global placement.

5. Preliminaries • [6] developed a simulated evolution-based global router. • Every multiple pin net is first decomposed into several two-pin nets. • Most two-pin net routings are completed by adaptive pseudo-random net-order routing (APRNOR). • Finally, a rip-up and reroute technique is applied to resolve overflow. • In this work, semi-routing is regarded as net decomposition and APRNOR.

6. Problem Formulation • Given an initial legalized placement with routing information (global bin size, capacity) and a global router. • Goal: Improve the placement by removing the congestion region to minimize overflow. If there is no any overflow, minimizing the routed wirelength is the main objective.

7. Algorithm

8. Algorithm • Model of Routed Wirelength

9. Algorithm • Congestion-driven Optimal Region • The region where a cell is placed to minimize its routed wirelength and congestion.

10. Algorithm

11. Algorithm

12. Algorithm

13. Algorithm • Cell Rearrangement by Bipartite Matching • Abipartite graph G=(V, E) with vertex classes X and Y • xi∈X denotes a cell; yj∈Y denotes a position; • edge e(i,j) represents the the edge connecting xi with yj, and the weight on edge e(i,j) is the total HPWL of all two-pin nets of cell xi when it is placed at position yj.

14. Algorithm

15. Algorithm • Cell Sorting Based Congestion Reduction

16. Algorithm • Pattern-PreRouting Based Congestion-Avoided Cell Shifting • Simulated Evolution-based Cell Selection • Congestion-Avoided Cell Shifting with Pattern PreRouting

17. Algorithm • Simulated Evolution-based Cell Selection

18. Algorithm • Congestion-Avoided Cell Shifting with Pattern PreRouting

19. Algorithm • Congestion-Avoided Cell Shifting with Pattern PreRouting

20. Experiment Results • The proposed placer was implemented in C/C++ language on an AMD Opteron 3.0GHZ with 32GB memory. • The ROOSTER[1] placers were run on the benchmarks as the input placement. The global router [6] was then run to measure the routability before placement refinement.

21. Experiment Results

22. Experiment Results

23. Conclusion • This work presents a placer that improves routed wirelengthand routability. • Experimental results show that the proposed placer can shortens routed wirelength on IBMv2 benchmark with other placer placement results.