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SEQUENCER DELAY PLD

SEQUENCER DELAY PLD. By ANTON H.C. SMITH ELECTRICAL ENGINEERING UNIVERSITY OF SOUTH CAROLINA. Roman Pot. Bellows. p. p. Detector. P 1 UP. P 2 OUT. S. Q2. Q3. Q4. Q4. Q3. Q2. S. D. D2. D1. P 1 DN. P 2 IN. A2. A1. 59. 57. 33. 23. 0. 23. 33. Z(m).

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SEQUENCER DELAY PLD

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  1. SEQUENCER DELAY PLD By ANTON H.C. SMITH ELECTRICAL ENGINEERING UNIVERSITY OF SOUTH CAROLINA

  2. Roman Pot Bellows p p Detector P1UP P2OUT S Q2 Q3 Q4 Q4 Q3 Q2 S D D2 D1 P1DN P2IN A2 A1 59 57 33 23 0 23 33 Z(m) Forward Proton Detector Layout • FPD is sub-detector of DØ consisting of 9 momentum spectrometers, allowing detection of scattered anti-protons and protons and determination of momentum and scattering angle • Central systems measured in DØ Detector

  3. Amp. Shaper FPD DFE L3 VRB FPD AFE Run I surplus Tester FPD SEQ DFE Contr. Run II standard MAPMT LMB FPD custom FPD TM L1 FW FPD LM PMT DØ LM FPD ELECTRONICS

  4. Analog Front End (AFE) • Basically the interface for the SVX chips • Files analog information into data stream • Digitalizes fiber information for Triggering • Allows algorithms that looks at hit patterns of fibers in detector to select valid tracks

  5. SEQUENCER • Real time manipulation of the control signal to the AFE to effect data acquisition,digitization, and readout based on the NRZ/Clock signals from the Controller.

  6. SEQUENCERCONTROLLER • It transforms Serial Command Link (SCL) signals into pairs of Sequencer control signals (NRZ &Clock). • These signals tell the Sequencer the proper times to reset the preamps, trigger,digitize, and read out data.

  7. Different Methods of Implementation SEQUENCER CONTROLLER • Delaying the Control Signals of the AFE • Delaying the NRZ signal on the Sequencer • Delaying the NRZ signal going to the sequencer from the Sequencer Controller NRZ SEQUENCER CONTROL SIGNALS AFE

  8. DELAY TIMES REQUIRED The theoretical delay times are: • 321ns • 575ns • 636ns

  9. Simple block diagram of Sequencer before modification

  10. Simple block diagram of Sequencer After modification

  11. Digital Logic 101 NOT 4-1 multiplex AND OR D-flip-flop 12 Bit Register

  12. Block Diagram of the NEW PLD

  13. Schematic of version1

  14. Schematic of Communication

  15. Schematic of NRZ delay Block.

  16. Schematic of programmable clock delay

  17. Conclusion How delays help the physics • Allows the FPD data be integrated into the system Simulation results show that • Min delay for Upper PLD is 188.8 ns • Max delay for Upper PLD is 414.4 ns • Min delay for Lower PLD is 494.8 ns • Max delay for Lower PLD is 720.4 ns • Resolution of about 5ns

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