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L1Calo PreProcessor Module

L1Calo PreProcessor Module. New MCM. We would like to develop a pin-, size- and latency-compatible substitute for the MCM based on today's components: AD9218 -- dual 105,MHz 10,bit FADC Xilinx Spartan-6 (SC6SLX45) FPGA in the CSG324 (15x15) package

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L1Calo PreProcessor Module

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  1. L1Calo PreProcessor Module

  2. New MCM • We would like to develop a pin-, size- and latency-compatible substitute for the MCM based on today's components: • AD9218 -- dual 105\,MHz 10\,bit FADC • Xilinx Spartan-6 (SC6SLX45) FPGA in the CSG324 (15x15) package • Functionality of ASIC, PHOS4 and LVDS Serialisers inside FPGA Modern reconfigurable device will allow us to adjust and to add new pre-processing algorithms (event-by-event pedestal subtraction, more sophisticated BCID algorithms, etc.) for higher luminosity expected after the LHC Upgrade

  3. LVDS Serializers • 480Mb/s serialisers for LVDS are implemented using Spartan-6 output serialiser blocks (OSERDES2). Eye-diagram shows a good signal quality:

  4. PprASIC • PprASIC (including serializers) verilog code is adopted and synthesized for the Spartan-6 FGPA. • Estimated power consumption: • FPGA: ~200 mW • ADC: ~275 mW per channel at 105MHz; ~1W on module

  5. nMCM PCB Layout • 10 layers design • Aim is to keep production technology as ''standard-and-simple'' as possible

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