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Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, 2002. A model for manual analysis. Simulation versus Model (NMOS). The square-law model doesn’t match well with simulations

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Digital Integrated Circuits A Design Perspective

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  1. Digital Integrated CircuitsA Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002

  2. A model for manual analysis

  3. Simulation versus Model (NMOS) • The square-law model doesn’t match well with simulations • Only fits for low Vgs, low Vds (low E-field) conditions Chris Kim

  4. Simulation versus Model (PMOS) • Not as bad as the NMOS device • Still large discrepancies at high E-field conditions Chris Kim

  5. Simulation versus Model (Ids vs. Vgs) • Saturation current does not increase quadratically • The simulated curves looks like a straight line • Main reason for discrepancy: velocity saturation Chris Kim

  6. Velocity Saturation • E-fields have gone up as dimensions scale • Unfortunately, carrier velocity in silicon is limited • Electron velocity saturates at a lower E-field than holes • Mobility (μe=v/E) degrades at higher E-fields • Simple piecewise linear model can be used Chris Kim

  7. Velocity Saturation [Toh, Ko, Meyer, JSSC, 8/1988] • Modeled through a variable mobility • n=1 for PMOS, n=2 for NMOS • To get an analytical expression, assume n=1 Chris Kim, Kia

  8. Velocity Saturation • Plug it into the original current equation Equate the two expressions to get Chris Kim, Kia

  9. Simulation versus Model • Model incorporating velocity saturation matches fairly well with simulation Chris Kim

  10. -4 x 10 2.5 VGS= 2.5 V Early Saturation 2 VGS= 2.0 V 1.5 Linear Relationship (A) D I VGS= 1.5 V 1 VGS= 1.0 V 0.5 0 0 0.5 1 1.5 2 2.5 V (V) DS Current-Voltage RelationsThe Deep-Submicron Era

  11. Perspective I D Long-channel device V = V GS DD Short-channel device V V - V V DSAT GS T DS

  12. -4 x 10 -4 x 10 6 2.5 5 2 4 1.5 (A) 3 (A) D D I I 1 2 0.5 1 0 0 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 V (V) V (V) GS GS ID versus VGS linear quadratic quadratic Long Channel Short Channel

  13. -4 -4 x 10 x 10 2.5 6 VGS= 2.5 V VGS= 2.5 V 5 2 Resistive Saturation VGS= 2.0 V 4 VGS= 2.0 V 1.5 (A) (A) 3 D D VDS = VGS - VT I I VGS= 1.5 V 1 2 VGS= 1.5 V VGS= 1.0 V 0.5 1 VGS= 1.0 V 0 0 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 V (V) V (V) DS DS ID versus VDS Long Channel Short Channel

  14. G S D B A unified modelfor manual analysis

  15. -4 x 10 2.5 VDS=VDSAT 2 VelocitySaturated 1.5 Linear 1 VDSAT=VGT 0.5 VDS=VGT Saturated 0 0 0.5 1 1.5 2 2.5 Simple Model versus SPICE (A) D I V (V) DS

  16. -4 x 10 0 -0.2 -0.4 (A) D I -0.6 -0.8 -1 -2.5 -2 -1.5 -1 -0.5 0 V (V) DS A PMOS Transistor VGS = -1.0V VGS = -1.5V VGS = -2.0V Assume all variables negative! VGS = -2.5V

  17. The Transistor as a Switch Eq added by Kia

  18. The Transistor as a Switch Eq added by Kia

  19. MOS CapacitancesDynamic Behavior

  20. Dynamic Behavior of MOS Transistor

  21. Polysilicongate Source Drain W x x + + n n d d Gate-bulk L d overlap Top view Gate oxide t ox + + n n L Cross section The Gate Capacitance

  22. Gate Capacitance Cut-off Resistive Saturation Most important regions in digital design: saturation and cut-off

  23. Gate Capacitance Capacitance as a function of the degree of saturation Capacitance as a function of VGS (with VDS = 0)

  24. Diffusion Capacitance Channel-stop implant N 1 A Side wall Source W N D Bottom x Side wall j Channel L Substrate N S A

  25. Capacitances in 0.25 mm CMOS process

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