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Tracking Electronics

Tracking Electronics. Marvin Johnson. SEQ. SEQ. SEQ. platform. HV / LV. Monitoring Control. 3/6/8/9 Chip HDI. 3M. Low Mass. IB. Optical Link 1Gb/s. Sensor. NRZ / CLK. 1 5 5 3. V R B. V R B. V R B. V R B. V B D. 68k. Bit3. VME. VRB Controller. PC. MPM. L3.

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Tracking Electronics

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  1. Tracking Electronics Marvin Johnson

  2. SEQ SEQ SEQ platform HV / LV Monitoring Control 3/6/8/9 Chip HDI 3M Low Mass IB Optical Link 1Gb/s Sensor NRZ / CLK 1 5 5 3 VRB VRB VRB VRB VBD 68k Bit3 VME VRB Controller PC MPM L3 DØ Silicon Data Flow Silicon Graphics

  3. Silicon System • Cables • Utilities • Bias voltage • DC power • Interlocks and alarms • Signal conditioning • Downloading • SVX sequencer • VME readout system • System testing

  4. 6 types of Cables • Kapton film from the detector (low mass, 8 ft long) • Clock is on separate twin coax • 80 conductor 3M pleated foil to interface card (30 ft) • Clock is on separate twin coax • 50 conductor 3M pleated foil to Sequencer (30 feet) • Fiber optic line from platform to MCH 2 (60 meters)

  5. Cable installation • Low mass cables come with the silicon • Connector adapter boards • 480 units • 2 ETF for 2 weeks + 10% supervisor • July 00 (aftr waveguides) • 80 conductor 3M cables • 456 units • 3 ETF for 5 weeks + 10% suoervisor • July -Aug 00 • 50 conductor 3M cables • 456 units • 3 ETF for 5 weeks + 10% supervisor • Jan - Feb 00 • Fiber optic cables • 600 units (includes CFT) • 3 ETF for 3 weeks • Dec 99 - Jan 2000 • Crew is E Podschweit + 2 new people

  6. Utilities • Interface crates • Provide utilities for silicon (signal conditioning, power, bias voltage etc.) • Located at the base of the calorimeter in all 4 quadrants • 2 ETF for 3 weeks • V. Martinez + new person • Jan 00 • Bias supplies • Uses existing D0 HV supplies • MCH work mostly complete • Patch panels on platform & jumpers to interface crate • 1 ETF for 3 weeks • J. Geralds • March 00

  7. DC power • Use common Vicor supplies (same as cal and other groups) for platform supplies • Interface supplies require mag. Shielding so use existing calorimeter design - all drawings exist • Sequencer power design is complete, drawings exist, supplies are on order. • 2 MTF for 3 weeks • Mar 00 • VRB system in MCH reuses supplies from run one including the control hardware. • 1 ETF for 3 weeks • V. Martinez

  8. Interlocks etc. • Interlock and control is the same as run 1 (1553 link to rack monitors). Almost all of this is already in place. • Downloading is also via the 1553 link. About 10 additional cables need to be installed from MCH to platform.

  9. Sequencer • Crates are here • Module production should start this week. • Testing • Iowa State - ETU 5 weeks • Mid Dec 99 • Installation • 1 ETF, 1EEF for 3 weeks • J. Green • M. Utes • Jan - Feb 00

  10. VRB’s • All modules are here and tested • 2 of 6 racks are being installed • All monitoring and control reuses run 1 equipment. • Installation • 2 EEF for 3 weeks • R. Angstadt • J. Anderson • Dec 99 - Jan 00

  11. System Test • U of Michigan is building an ‘SVX Emulator’ board • Completely emulates the digital part of the SVX. • Allows down loading of fake events and read out at full speed. • Includes readout of bias voltage, supply voltage and downloaded parameters, • Building enough for 1/8 of the detector. • Can connect at the sequencer, interface crate or adapter crate on CC • Allows complete system testing all the way through L3 including the online software and monitoring. • Commissioning • PF, EEF for 4 weeks • M. Utes + New Physicist • Jan - Mar 2000

  12. Fiber tracker • Analog processing • Digital processing • Trigger (covered by G. Blazey) • VRB Read out (same as silicon)

  13. Fiber electronics

  14. Analog Front End • Located on cryostat • Uses trigger pickoff chip in front of SVX II chip • Difficult design (5 fC trigger level) • 2 versions 8 and 12 chip • First layout of 8 chip finished but extensive revisions • Expect next prototype feb 1,2000 • If no revisions, 10 boards in April, 2000 • 12 chip is delayed (difficult layout) • probably 2 months beyond the 8 chip • Infrastructure (crates, backplanes, power etc) are designed and most are on order

  15. Analog testing • LED pulser for board and system test • Pulse individual fibers with variable amplitude and time. • 512 channels are available. • Can test both fiber and preshower systems • Can test boards either in a test station or on the cryostat • Mixer board precludes trigger testing • Pulser system is done except for the connection to the test stand. • Board testing either by Iowa State or Fermilab.

  16. Analog boards • Installation • Limited by Cassette production • 2 ETF for 4 weeks • O. Payne • V. Martinez • May - Sept 00 • Commissioning • 2 EEF, 2 PF for 8 weeks • P. Sheahan • J. Anderson • S. Gruenendahl • detector groups • May - Sept 00

  17. Digital boards • one board + 2 daughter boards for all L1 and L2 front end data • Mother board and first daughter board nearly complete • Second daughter board in layout • Prototype communications system works very well • Design is basically large FPGA chips and comm links so low risk.

  18. Digital testing • Reprogram the digital front end board to send out test patterns. • Can test all down stream systems all the way to L3 • Use same boards as pattern generators for board testing • Request into PREP for initial testing and maintenance • Comm. link uses serial protocol so modest number of cables • Power supply, backplanes etc. are designed and most are on order. A

  19. Digital boards • Installation • 2 ETF for 4 weeks • O. Payne • V. Martinez • Mar - Apr 00

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