Update on the Tracking Chamber and Readout Electronics

1. Update on the Tracking Chamber and Readout Electronics University of Houston

2. Electronics update • The short straw prototype has been upgraded and repaired: • New flexible cables for anode signals and loose wires repaired • ASD preamp board and shielding box completed; • 32 channel anode board and 32 channel cathode board with adjustable gain completed • 32 channel timing output with ECL driver completed • DAQ program and trigger system completed • After 3 month of discussion and work with LBNL, we now have 28 ELEFANT chip samples (~200 channel). • A 64-channel digitizer front -end system is under design. Components selection is completed, FPGA simulation design is completed, and board design begun. • Alternative cathode strip designs are being considered. • We have all licenses for CMOS mixed signal chip design, and we are able to use MOSIS and Cadence. E. Hungerford Update on the Tracking Chamber and Readout Electronics

3. SP-II upgrade • Redesign the connection and protection for anode flex cable • ASD shielding box is completed • Prototype improved and repaired • 32 channels of A and of T electronics working E. Hungerford Update on the Tracking Chamber and Readout Electronics

4. MDAQ-2 • Installed on a 2.4GHz Linux PC system, connected to a single board computer (SBC) module, MVME-5100-0161, located in a 7-slot-VME-mini-crate. • Wiener VC32 interface VME module connects to Wiener CC32 CAMAC controller • CODA system and VxWork software. • Real time trigger interface installed • LeCroy ADC 2249 run-control test succeeded. Events recorded at rates up to a few kHz. E. Hungerford Update on the Tracking Chamber and Readout Electronics

5. Horizontal Perpendicular The induced charge distributions on the pads are wider than expected • The predicted distribution is a spread on ~3 pads. This is observed for the distribution when horizontal to straw (Mathieson (NIM 227A, 1984). • Perpendicular to the straw the charge spreads over 7strips E. Hungerford Update on the Tracking Chamber and Readout Electronics

6. Two possible scheme of readout • In order to reduce the channel number of readout pads if the Z resolution is reduced (~1.5mm), two methods are considered. • A highly segmented cathode pad readout was developed 12 years ago. With printed resistive ink on the pads, Z- resolution is 100um to 1000um corresponding to 1pC to 100fC anode charge. • A chevron pad readout has also been investigated. The position resolution is approximately the same. • These methods can reduce the total channel number by 1/2 Resistive straw & Pads Chevron Pads Segmented pads readout (1991) 12mm E. Hungerford Update on the Tracking Chamber and Readout Electronics

7. NI PCI-6534 Data Transmitter & Command Receiver (CPLD) DAC 16k FIFO Elefant Gain Readout Sequencer Shaper ASD TXer 8 L.Conv ADB Controller 8x2 Clock 60MHz Trigger Decision Hit point Multiplexer (CPLD) 4 ADB CMB external trigger input Digitizer front-end prototype System • This system consists of 64 channels preamplifier boards, ADB boards, CMB board, and PC. • 4 ADB boards, each one accepting signal from a 16-channel preamplifier board, are plugged into a CMB board. • A CMB board controls the whole system, collects data from Elefant chips, and sends them to a PC thru a NI high speed DIO board. • Preamplifier board design is done. The schematic file input for ADB is finished. FPGA and CPLD design for CMB board is done and schematic design will start soon. • This design will be reported On 2003 IEEE Nuclear Science Conference. E. Hungerford Update on the Tracking Chamber and Readout Electronics

8. not A not B A B D Q CLK Programmable Logic Device • PLD • First Programmable Logic chip • A set of fully connected macrocells, which are typically comprised of some amount of combinatorial logic (AND and OR gates, for example) and a flip-flop • Address decoder • CPLD – Complex PLD • Density increased, multiple PLD with additional interconnection • Signal delay is predictable and short • More complicated logic design, high performance logic design • FPGA • A large amount of macrocells (logic block), flexible interconnection, programmable I/O block • Flexible than CPLD • register-heavy and pipelined applications, the fast processing of data streams. • In place of a processor-plus-software solution. E. Hungerford Update on the Tracking Chamber and Readout Electronics

9. a out b What’s VHDL? • Very High Speed Integrated Circuit Hardware Description Language • Describe the structure and behavior of digital electronic hardware designs • IEEE Std 1076-1987 and 1076-1993 • Support top down, bottom up design methodology, like C language VHDL Programming library ieee; use ieee.std_logic_1164.all; entityplus2 is port ( a, b : std_logic; out : std_logic); end plus2; architecture a1 of plus2 is begin out <= a + b; end a1; Truth Table E. Hungerford Update on the Tracking Chamber and Readout Electronics

10. State-machine E. Hungerford Update on the Tracking Chamber and Readout Electronics

11. VHDL Design Flow Input of your design Transformation of an abstract description into detailed gate level description Ex. A + B A exclusive-or B Map design into the target device Download design into the target device E. Hungerford Update on the Tracking Chamber and Readout Electronics

12. NI PCI-6534 Data Transmitter & Command Receiver (CPLD) DAC 16k FIFO Elefant Gain Readout Sequencer Shaper ASD TXer 8 L.Conv ADB Controller 8x2 Clock 60MHz Trigger Decision Hit point Multiplexer (CPLD) 4 ADB CMB external trigger input Digitizer front-end prototype System • This system consists of 64 channels preamplifier boards, ADB boards, CMB board, and PC. • 4 ADB boards, each one accepting signal from a 16-channel preamplifier board, are plugged into a CMB board. • A CMB board controls the whole system, collects data from Elefant chips, and sends them to a PC thru a NI high speed DIO board. • Preamplifier board design is done. The schematic file input for ADB is finished. FPGA and CPLD design for CMB board is done and schematic design will start soon. • This design will be reported On 2003 IEEE Nuclear Science Conference. E. Hungerford Update on the Tracking Chamber and Readout Electronics

13. FPGA ADB Controller Design Function • After power on, FPGA generates RESET signal to initialize the EES system to a known state. After that, FPGA generates SYNC signal periodically to synchronize the TDC counters in all the Elefant chips. • When an coincident event happens, generate a L1_Accept signal. This signal starts Elefant chips to move data from latency buffer to an event buffer • To simplify the design, after the generation of a L1_Accept, FPGA waits for a specific time. During that time, the Elefant chips move data of current event from latency buffer to an event buffer. So, the FPGA is insensitive to the new coincident event in this waiting state. • After this period of time, FPGA starts a readout process to read data from Elefant (with or without zero suppression), build an event data frame, and write it into FIFO. • During the process of readout, if there’s new coincident event, FPGA saves the appropriate event flag in a buffer temporarily. When the current readout completed, FPGA starts the new process to readout this saved event. E. Hungerford Update on the Tracking Chamber and Readout Electronics

14. FPGA ADBC Structure Sync Reset SPI Elefant Control Signal Vth Sel, CS … Reset & Sync Generation Readout Sequencer Logic SysClk Clk15 Generation typerdadb_stateis ( idle, -- clock => to do initialize, -- 1 => write start of data frame readhitmap, -- 1 => read hitmap from a ADB asserthitmap, -- 1 => see if hitmap is empty writeADBnum,-- 1 => write ADB, elefant addrs. writehitmap, -- 1 => write hitmap readtag, -- 1 => readout tag readcounter, -- 1 => readout counter writechannelnum, -- 1 => write channel number readstart, -- 1 => readout data readincword, -- n nextchannel, -- 1 => increase channel number nextelefant, -- 1 => increase elefant number incbuffrd); -- 1 => increase buff_rd pointer Data to FIFO Trigger Decision Making Logic Control L1_Accept 16 Trigger pattern WR Buf RD Buf 16 2 2 8 scintillator Wr_addr Rd_addr Data from Elefant E. Hungerford Update on the Tracking Chamber and Readout Electronics

15. Waveform of ADBC FPGA is designed using VHDL. We select Xilinx Spartan-II product as the device. All the simulation is done in Xilinx Integrated Development Environment. The waveform is shown in the following window. This waveform matches the waveform of Elefant chip. It makes sure that FPGA will work functionally. E. Hungerford Update on the Tracking Chamber and Readout Electronics

16. Waveform of Data Transmitter (TXer) TXer is designed using VHDL and implemented in a Xilinx CPLD. It transfer data from FIFO to PC through a parallel data bus with the speed up to 20MHz. It also receive command from PC and does the appropriate configuration through the serial bus between the CMB board and ADB boards. This transceiver design is done. The following window shows the simulation waveform. It matches the NI high speed DIO input timing waveform and TI FIFO output waveform. E. Hungerford Update on the Tracking Chamber and Readout Electronics