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ASIC buck converter prototypes for LHC upgrades

ASIC buck converter prototypes for LHC upgrades. S.Michelis 1,3 , C. Azra 3 , B.Allongue 1 , G.Blanchot 1 , F.Faccio 1 , C.Fuentes 1,2 , S.Orlandi 1 1 CERN – PH-ESE 2 UTFSM, Valparaiso, Chile 3 EPFL, Lausanne. Outline. Introduction AMIS2 Features Pinout Waveforms Efficiency

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ASIC buck converter prototypes for LHC upgrades

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  1. ASIC buck converter prototypes for LHC upgrades S.Michelis1,3, C. Azra3,B.Allongue1, G.Blanchot1, F.Faccio1, C.Fuentes1,2, S.Orlandi1 1CERN – PH-ESE 2UTFSM, Valparaiso, Chile 3EPFL, Lausanne

  2. Outline • Introduction • AMIS2 • Features • Pinout • Waveforms • Efficiency • Radiation results • Noise performances • IHP1 • Features • Conclusions 2 S.Michelis CERN/PH

  3. Detector DC/DC Power distribution scheme • DC/DC converter requirements: • Vin= 10-12V • Vout= 1.8-2.5V • Switching frequency ~ MHz • due to magnetic field • Rad-hard design • 250Mrd, 2∙1015 n/cm2 • Buck converter is the chosen topology: • high efficiency • small number of external components 1.8-2.5V Power supply 10-12V 3 S.Michelis CERN/PH

  4. First ASIC: AMIS1 • FEATURES • VIN and Power Rail Operation from +3.3V to +24V • Includes basic building blocks • External oscillator Programmable from 250kHz to 3MHz • External voltage reference • Vertical HV transistors are used as power switches • PROBLEMS • Low efficiency due to overlap between gate signals for power mosfet. 4 S.Michelis CERN/PH

  5. Second ASIC: AMIS2 • FEATURES • VIN and Power Rail Operation from +3.3V to +12V • Internal oscillator fixed at 1Mhz, programmable up to 2.5MHz with external resistor • Internal voltage reference • Programmable delay between gate signals • Integrated feedback loop with bandwidth of 20Khz • Different Vout can be set: 1.2V, 1.8V, 2.5V, 3V, 5V • Lateral HV transistors are used as power switches • Enable pin 5 S.Michelis CERN/PH

  6. AMIS2 circuit details (1) • Bootstrap circuit needed to drive the high side switch (SW1) whose source is floating • An external bootstrap capacitor is needed • Cboot > CgSW1 x10 • CgSW1=7.5nF (W=0.15m) Gate SW1 Voltage Phase Sw1 on Vin Sw1 on SW1 off time SW1 Gate SW1 Bootstrap capacitor L Vout Phase Cout 3.3V SW2 Input signal S.Michelis CERN/PH

  7. AMIS2 circuit details (2) Bandgap provides a constant reference voltage over temperature variations and radiation effect S.Michelis CERN/PH

  8. AMIS2 circuit details (3) The integrated control loop guarantees the stability for input and load variations S.Michelis CERN/PH

  9. + - + - AMIS2 chip layout Vin Sawtooth generator CBTSR SW1 SW1 • The chip size is 3x3 mm • The biggest part is reserved to power transistors driver Vo L SW2 Cout SW2 Drivers Bandgap CONTROL Comparator EA Driver logic+ bootstrap Bandgap Sawtooth generator 9 S.Michelis CERN/PH

  10. Package QFN48 Package QFN32 7 mm 5 mm 7 mm 5 mm AMIS2 pinout POWER • Several pins for power transistors. • Red pins for the control circuit for testing • QFN48 for testing • QFN32 for system level test CONTROL 10 S.Michelis CERN/PH

  11. Sw1 on Sw1 on SW1 off AMIS2 Waveforms Waveforms of the input and output voltage, the voltage at the inductor node (Phase) and the gate signal for SW1. 11 S.Michelis CERN/PH

  12. AMIS2 efficiency • The measured efficiency goes up to 82%, depending on load current and frequency. • Conductive losses are the major contribution of inefficiency. • Resistance along the current path is much higher than the one expected for the power transistors alone. This is due to on-chip routing and bondings. 12 S.Michelis CERN/PH

  13. Mos resistance Bonding RBond=80mΩ Metals RM=50mΩ Silicon RSi=30mΩ Package QFN48 Total resistance Rtot=RSi+RM+RBond=160mΩ (more than RSi x 5) Big impact of bondings and metal routing QFN32 will reduce a bit the bonding resistance Final integration maybe with flip chip. It can drastically reduce the conductive losses

  14. AMIS2 Radiation results The X-ray radiation tests shows a decrease of the efficiency mostly due to the radiation induced leakage current , compensated by the threshold voltage shift. Pre rad Annealing 3 days Annealing 7 days 14 S.Michelis CERN/PH

  15. Typical application π filter π filter Linear Regulator AMIS2 15 S.Michelis CERN/PH

  16. Noise tests with AMIS2 • The AMIS2 power ASIC was mounted on 3 different prototypes: same schematic, different layouts. • PCB and Coilcraft coils were tested. • Several placements were exercised. • CM, DM and LISN figures were acquired. • The reference setup was used. • Load = 0.9A x 2.5V, Switch frequency = 1.55 MHz. S.Michelis CERN/PH

  17. AMIS2 Tests: Layout AMIS2 V2 AMIS2 V3 AMIS2 V1 In/Out on opposite sides In/Out on corner sides In/Out on corner sides Filters on opposite sides Coil along Y axis Coil along X axis Filters close together Filters further closer With inductors S.Michelis CERN/PH

  18. Best noise performances Best noise performance of AMIS2 CM DM Evolution of noise performance of prototype with commercial components Proto2 Proto3 Proto5 CM CM CM 18 S.Michelis CERN/PH

  19. Third ASIC: IHP1 • We moved on a 0.25um technology from IHP. • Tests shows that this technology has better performance • for radiation tolerance for TID and displacement damage • (see talk of F. Faccio during Power WG) • for efficiency (lower on-resistance and capacitance) • A new buck design has been submitted in May 2009 and chip will be back this week • FEATURES • VIN and from +2.5V to +12V • Internal oscillator fixed at 2Mhz, programmable • External voltage reference • Adaptive logic for optimum gate delay • External feedback loop with bandwidth of 20Khz • Enable pin • Package QFN48 19 S.Michelis CERN/PH

  20. Conclusions • AMIS 2 has been tested and it shows good performances in term of • Efficiency: up to 82% • Noise: compliant with class A CISPR 11 standards and close to class B limit. • Radiation: after annealing only 2% of efficiency is lost in the worst case (Vin=10V and TID=300Mrd) • We have now moved to a 0.25um technology and first prototype has been delivered this week 20 S.Michelis CERN/PH

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