290 likes | 431 Views
Statistical guarantees of performance for MIMO designs. Jayanand Asok Kumar Shobha Vasudevan University of Illinois at Urbana Champaign. MIMO systems. Digital communication systems At the physical layer: Transmit and receive data bits Operation at high data rates is required
E N D
Statistical guarantees of performance for MIMO designs Jayanand Asok Kumar Shobha Vasudevan University of Illinois at Urbana Champaign
MIMO systems • Digital communication systems • At the physical layer: Transmit and receive data bits • Operation at high data rates is required • Bit Error Rate(BER) is a performance metric • Bit error: Decoded bit does not match actual data bit • BER: Average probability of a occurrence of bit errors • Multiple Input Multiple Output (MIMO) systems • Complex wireless communication systems • Comprise several components implemented at the Register Transfer Level (RTL) • Components must meet area and power requirements as well MIMO RTL design is both time and resource-intensive
Performance estimation • Traditionally, hardware is viewed as non-probabilistic • Data corruption at the receiver • Thermal noise, quantization etc. • Introduces randomness into the RTL designs • Performance metrics are probabilistic in nature • Simulation-based techniques • Reasonably accurate performance estimates • Time-consuming and incomplete • Need to estimate performance quickly and with a high degree of confidence We employ probabilistic model checking
Sources of randomness • Analog to Digital Converter (ADC) • Discretizes signal in time (sampling) and value (quantization) • Imperfections in circuitry • Thermal fluctuations in current and voltage • Timing errors at the sampler • Lumped together and referred to as noise • Signal to Noise Ratio (SNR) • Provides a measure of the level of noise We assume an Additive White Gaussian Noise (AWGN) model
Error modeling • External data corruption errors • Incorrect quantization level due to signal noise • Internal data corruption errors • Insufficient precision (number of bits) for data representation • Eg: Both values 0.95 and 0.55 represented by 0.75 • For a given q[n], bit decoding is non-probabilistic • Can map q[n] to bit errors by analyzing RTL code Area = probability Gaussian curve determined by SNR Value of q[n]
Our methodology pCTL: probabilistic Computational Tree Logic • We use PRISM, a symbolic model checker Potentially leads to state-space explosion Best, worst and average case Sound techniques applicable to a large class of systems Rigorous analysis for performance estimation
Case studies: MIMO systems • Case studies using components of MIMO systems I Error properties of a Viterbi decoder II Error properties of a MIMO detector IIIConvergence properties of a Viterbi decoder We assume Binary Phase Shift Keying (BPSK) signaling
Viterbi decoder basics • x[n] : Data bit at time step n • System has memorym=1 • q[n] : Received quantized sample • Insufficient to decode “most likely” transmitted bit • Viterbi decoder waits for L-1 time steps • L is traceback length • Heuristic choice: L > 5m (We choose L = 6) • Decodes bit using most likely “sequence”
Viterbi algorithm • Pathmetrics pm0, pm1: Cost of paths • prev0, prev1: Most probable previous internal state • 1 time step = 1 clock cycle = 1 trellis stage • Decoding: • Trace back along path with least cost • Decoded bit ≠ actual data bit (Bit error!) • Latency of L-1 cycles pm0 Internal State 0 Decodes bit 0 prev0=1 Actual data bit pm0 < pm1 prev1=0 Internal State 1 pm1 Depend on q[n]
DTMC modeling • DTMC model M: • State variables S (spans L trellis stages) • State μ: Unique assignment of values to S • State transition relation TP: S x S→[0,1] • State variable flag = 1 if decoded bit ≠ xL-1 0 otherwise Stage L-1 Stage L-2 Stage 0 pm0 prev0L-2 prev00 prev0L-1 prev01 xL-2 xL-1 x0 x1 prev1L-2 prev10 prev1L-1 prev11 pm1 Current stage Next clock cycle
State transition relation TP • DTMC transition: State μ→ State μ’ • Probabilistic updates (pm0’, pm1’, x0’) = Γp(pm0, pm1, x0) • Probability computed based on x0and q0 (from SNR) • Non-probabilistic updates (prev00’, prev10’) = FS (pm0’, pm1’) Shift trellis to the right: (prev0i+1’, prev1i+1’, xi+1’) = (prev0i’, prev1i’, xi’), 0 ≤ i ≤ L-1 Traceback operation: flag’ = FE(prev0i’, prev1i’, xL-1) Above functions collectively define TP
Property specification • We define a reward model on DTMC M • Assign a reward equal to value of flag in a state • P2(Average case): R=? [I = T] • Probability that an error occurs at the Tth step • In steady state, P2 corresponds to BER • P1 (Best case): P=? [G ≤ T (! flag)] • Probability that no error occurs in T steps • P3 (Worst case): P=? [F ≤ T (flag >1)] • Probability that more than 1 error occurs in T steps P1, P2 and P3 together can be used to make stronger claims about error-related performance of system
Property-preserving reduction • For error properties • Actual value of decoded bit is not required (Data abstraction) • Replace prev0, prev1,x with c, w (data abstraction) (ci’, wi’) = Fabs (prev0i’, prev1i’, xi’), 0 ≤ i ≤ L-1 • c, w indicates “correctness” of traceback operation • Can discard variables storing past data bit values • Reduction in number of possible states Stage L-1 Stage L-2 Stage 0 pm0 cL-2 c0 cL-1 c1 xL-2 xL-1 x0 x1 wL-2 w0 wL-1 w1 pm1
Reduced DTMC MR • Probabilistic function Γp is preserved (pm0’, pm1’, x0’) = Γp(pm0, pm1, x0) • Modified non-probabilistic updates (c0’, w0’) = Fcw(pm0’, pm1’) Shift trellis to the right: (ci+1’, wi+1’) = (ci’, wi’), 0 ≤ i ≤ L-1 Traceback operation: flag’ = FER(ci’, wi’, x0’) • flag still indicates correctness of decoded bit Reduction can be applied to systems with decoding latency
Proof of correctness • Reduction is sound with respect to error properties • Proof involves showing two parts Part A) Value of flag is the same in both μ and μR Part B) P (μ→μ’) = P(μR → μR’) MR is a probabilistic bisimulation of M Fabs: Equivalence relation
Probabilistic model checking • Verify properties P1, P2 and P3 on DTMC model MR • Probabilistic model checking • Explores all possible paths of length T High-confidence performance estimates can be obtained
MIMO system: Channel • MIMO system: • NR receive antennas, NT transmit antennas y = Hx+ n y: Vector of NR received signals x: Vector of NT transmitted bits H: NRxNTChannel matrix (Rayleigh flat-fading) n: Noise vector (AWGN) H can be assigned complex values
MIMO detector • Maximum Likelihood (ML) detection • Estimate most likely x, given y Estimate = arg min |y-Hs| where s is a possible value of x • Consider a 2x2 MIMO system with BPSK Split into real and imaginary parts: Estimate = arg min (|y1,R – h11,Rs1 – h12,Rs2| + |y1,I – h11,Is1 – h12,Is2| + |y2,R – h21,Rs1 – h22,Rs2| + |y2,I – h21,Is1 – h22,Is2|) = arg min (M1,R + M1,I + M2,R + M2,I) where s1, s2 are elements of s DTMC state variables
Symmetry reduction State μ’ State μ • M1,R in stateμ = M2,R in stateμ’ • M1,RandM2,Rare symmetric with respect to MIN block • Receiver blocks are structurally symmetric • Well-known symmetry reduction techniques can be applied
Convergence in a Viterbi decoder • Traceback paths converge • Decoded bit is independent of starting state • Typically, L > 5m is chosen • Convergence is a measure of confidence in the decoded bit • Convergent stage: prev0 = prev1 • Introduce the state variable count into M • count = count + 1 if stage is not convergent • If count > L, set flag =1 and reset count to 0. • Define a reward model on DTMC M using flag
Convergence property • Property specification • C1: R=? [I = T] (similar to P2) • Probability that the decoded bit has non-converging traceback paths • Property-preserving reduction • Values from only the current trellis stage are required • State variables in MR : pm0, pm1, x0, flag and count • State transition relation: Γp is preserved from M Reduction techniques depend not just on the type of the system, but also on the property to be checked
Results: Case study I • P2 matches BER from simulations • Reachability Iterations (RI) • PRISM explores all reachable states of DTMC • T > RI is sufficient for convergence of result • Faster than computing Steady State (SS) rewards RI = 263
Results: Case study II • Model checking times • Time-bounded approach: < 0.5 seconds, for each T • SS reward computation: 53.27 seconds • Simulation-based computation • BER = 1.07x10-5 using 107 time steps • No bit errors found using 105 time steps! RI = 3
Results: Case study III • MR has 61,000 states (Runtime: 120 seconds) • C1 stabilizes for L > 5 RI = 77
Future work • Error diagnosis mechanism when a property fails • Characterization: Is corruption external or internal ? • In the absence of internal data corruption, a correct quantization level results in a correct decoded bit • Structural changes: (eg: Increase precision) • Remove internal data corruption • Analyze the effects of hardware faults • Hard and soft errors • Incorporate compositional reasoning to improve the scalability of our methodology