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A DSP Enabled Microsystem for Cochlear Implants with Hybrid LC Clocking

Telemetry coil, RF interface, ADC, voltage regulator. Hermetic vacuum package. Flexible polyimide cable. 128-site high density electrode array. Back-end electronics, current sources, communication interface. A DSP Enabled Microsystem for Cochlear Implants with Hybrid LC Clocking.

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A DSP Enabled Microsystem for Cochlear Implants with Hybrid LC Clocking

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  1. Telemetry coil, RF interface, ADC, voltage regulator Hermeticvacuumpackage Flexible polyimide cable 128-site high density electrode array Back-end electronics,current sources,communication interface A DSP Enabled Microsystem for Cochlear Implants with Hybrid LC Clocking

  2. CIS DSP Core • 16 channels • Expandable architecture • Reduced datapath width • 3MHz operation with 22kHz front-end ADC • 3,000 pulses per second per channel maximum • Four operating modes • Programming • Stimulation • Test • Sleep

  3. 3.03mm Microsystem Measured Results • TSMC 0.18mm MM/RF bulk CMOS • 1.79mW from 1.2V is lowest reported DSP power consumption • Add 22kHz 16-bit ADC in future

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