A Lithography-friendly Structured ASIC Design Approach

1. A Lithography-friendly Structured ASIC Design Approach By: Salman Goplani* Rajesh Garg # Sunil P Khatri # Mosong Cheng # *National Instruments, Austin, TX 78759 # Department of ECE, Texas A&M University, College Station, TX

2. Outline • Motivation • Mask costs increasing • Systematic process variations increasing • Previous Work • Our Approach • NAND2 based circuit implementation methodology • Experimental Results • Conclusions

3. Motivation – Mask Costs • A full set of lithography masks can cost between $1-3M. • Roughly 25% reduction in ASIC design starts in past 7 years. [Sematech Annual Report 2002], [ A. Sangiovanni-Vincentelli “The Tides of EDA”, keynote talk, DAC 2003]. • Need an approach in which different designs share a set of masks

4. Motivation - Variations • Process variations can be classified as • Random variations • Systematic variations • Random variations are unpredictable • Caused by random fluctuations such as number of dopant atoms • Systematic variations • Predictable variation trends across a chip • Caused by spatial dependencies during device processing • Chemical and mechanical polishing (CMP) • Optical proximity effects (OPE) • Changes in poly shapes translates into channel length variations • Impacts circuit performance more severely compared to metal variations

5. Motivation – Structured ASICs • Standard cell based design approach (ASIC) • Severely affected by OPEs due to lack of regularity in design • Optical proximity correction (OPC) is performed to deal with OPEs • OPC needs to be performed on all layers for each new ASIC design • Computationally expensive process • Need a circuit design approach that • Allows us to share a majority of fabrication masks across different designs • Allows us to share the OPC computation for some layers, across different designs • Our approach achieves these goals

6. Previous Work • Jayakumar et. al. 2004 proposed a structured ASIC approach using a network of fixed (medium) sized PLAs • Large delay (area) overhead of ~260% (~240%) • Gulati et. al. 2007 reported a pass transistor logic (PTL) based structured ASIC approach • Delay and area overheads are ~50% and ~240% • Pillegi et. al. 2003 reported that FPGAs are typically ~25X slower than ASICs • Our approach provides a structured ASIC solution with small area (~10%) and delay (~35%) overheads

7. Our Solution • Use a regular array of 2-input NAND cells as the underlying circuit structure, and customize only METAL and VIA masks • NAND2 is functionally complete • Stock such arrays pre-processed until metallization step • Or, use previously generated masks for all other layers and use new masks for only METAL, VIA layers • To create an ASIC for a given design – technology-map this design to the smallest available NAND2 array • Only METAL and VIA masks require changes • Easier to fix bugs, since only METAL and VIA masks change • Optimize poly layer mask for maximum yield • Perform aggressive OPC on the poly layer • Required to be done only once • Beneficial since performance highly sensitive to channel length variations

8. NAND2 Cell Array • NAND2 cells are placed to create rectangular array of cells • Some space is left between two rows of NAND2 cells • Used for routing

9. NAND2 Cell • Size- 1.6mm X 2.6mm • Input/output pins on Metal1 • Symmetrical along vertical axis up to poly layer • Placer can map to original or flipped cell orientation, thereby reducing area • Poly and diffusion layers unchanged if a cell is flipped, hence same masks used for either orientation. • Layout of NAND2 cell is lithography-friendly • No bends in poly • Poly on a fixed pitch (as required in more recent fabrication processes) • Good for manufacturability reasons

10. Circuit Mapping to NAND2 Array • Library L consists of 1X, 2X, 3X and 4X NAND2 cells • 2X, 3X and 4X NAND2 cells are implemented by connecting 2, 3 and 4 NAND2 cells in parallel N* Combination circuit N in blif format Technology indep. opt. of N Map N* with L for area or delay N1 Place N2using QPLACE -SEDSM and Route using WROUTE Replace all 2X, 3X or 4X NAND2 cells in N1 by 2, 3 or 4 1X NAND2 cells N2

11. Characterization of NAND2 Array • Delay (D) is obtained using the sense package in SIS • Sense reports the largest sensitizeable delay of the circuit (excludes any false paths) • We use gate netlist N1 with 1X, 2X, 3X and 4X NAND2 • Power - dynamic power of a circuit is • f (= 1/D) is the operating frequency of circuit • Ceff is the total switching capacitance where: Ck is the capacitance of the node k is the probability of transition of the node k

12. Characterization of NAND2 Array • Transition probability of the node k is given by where: pk is the probability that node k is at logic “1” • Probability pk is obtained using the approach of Gulati et. al. 2005 • pk = 0.5 for primary inputs • For any node, obtain pk by propagating input probabilities based on node functionality • Area is obtained by placing and routing N2 using SEDSM tools from Cadence • All benchmark circuits are routed using up to 4 Metal layers

13. Characterization of NAND2 Array • OPC and lithographical simulations • Used Calibre tool from Mentor Graphics • We used optical model with l = 193nm • Constant threshold resist model was used • We perform OPC on poly and metal layers (referred to as M) of the placed and routed N2 design. Resulting layers are referred to as MOPC • Lithographical simulations are then performed on all layers in MOPC to obtain resulting layers MSIM • Error is the area of layer EM which is given by EM = XOR(M, MSIM)

14. Experimental Results • Designed NAND2 cells library L using 100 BPTM with VDD = 1.2V • Also implemented standard cell library LSTD • L contains 1X, 2X, 3X and 4X NAND2 cells • LSTD consists of INV and NAND, NOR, AND & OR gates (with 2 and 3 inputs) • Implemented several ISCAS and MCNC benchmark circuits using our approach and ASIC approach • We mapped these designs for both area and delay optimality

15. Area, Delay and Power • Average results for several circuits implemented using our NAND2 structured ASIC approach and traditional ASIC approach • Detailed results in paper

16. Lithography Simulation • Ratio of lithographical error for poly and Metal1-4 layers for both approaches • Errors on poly and Metal1 for our approach is lower than ASIC approach • Poly error translates into channel length variations • Sheet resistivity of Metal1 is higher than Metal2-4 • Wires in these layers is largely restricted to within the cell alone • Our approach uses more wiring on Metal2-4 due to an overall area increase, resulting in an increase in error on these layers

17. Conclusions • With increasing cost of masks and process variations • Need to implement circuits using regular structures • We presented a new structured ASIC approach • Implements circuits using regular array of 2-input NAND gates • Our approach has small overheads compared to standard cell (ASIC) based design approach • Area - 12% • Delay - 40% • Power - 7% • Lithographical errors of our approach are lower on poly and Metal1 layers by 7% and 24% compared to ASIC approach • Our approach is lithography friendly

18. ` Thank You!!

19. Backup Slides

20. AREA

21. Delay

22. Power

23. Lithographical Error

24. Implementing Sequential Circuits • Flip Flop can be implemented using NAND2 gates as shown

25. Circuit Mapping to NAND2 Array • Library L- 1X, 2X, 3X and 4X NAND2 cells • 2X, 3X and 4X NAND2 cells are implemented by connecting 2, 3 and 4 NAND2 cells in parallel • Circuit mapping N2 Combination circuit N in blif format Mapped Circuit N2 using only 1X NAND2 SIS Replace all 2X, 3X and 4X NAND2 cells by 2, 3 and 4 1X NAND2 Cells Technology Indep. Opt. of N N* Map N* with L for Area and Delay N1