Dynamic Fraction Control Bus: New System-on-Chip Communication Architecture Design

1. Dynamic Fraction Control Bus: New System-on-Chip Communication Architecture Design University of Louisiana at Lafayette Center for Advanced Computer Studies Nan Wang and M. A. Bayoumi IEEE SOCC 2005 INTERNATIONAL

2. Outline • Introduction & Motivation • Existing On-chip Communication Architectures • New Architecture Design • Test results • Conclusion IEEE SOCC 2005 INTERNATIONAL

3. Keywords • PEs- Processing Elements • OCA- On-chip Communication Architecture • Master Components– the Components that can initiate a communication transaction • Slave Components– the Components that can only respond to the communication request • FCB– Fraction Control Bus IEEE SOCC 2005 INTERNATIONAL

4. Introduction& Motivation • General SOC System IEEE SOCC 2005 INTERNATIONAL

5. Introduction& Motivation • Provides Reuse Environment -- Module reused, IP, open source code -- Architecture reused, on-chip bus -- Verification reused, IP cores, VCs IEEE SOCC 2005 INTERNATIONAL

6. Introduction& Motivation • Importance of Communication Architectures 1. Increasing system Complexity 2. Global Interconnects dominate performance/ power/ reliability 3. Increasing Availability of configurable Communication IP, feasibility for OCA selection IEEE SOCC 2005 INTERNATIONAL

7. Introduction& Motivation • Communication Architecture design Issues -- Communication Topology system shared bus, hierarchical bus structure, ring, mesh, custom bus networks -- Communication Protocols static priority, TDMA, Round robin, token passing -- Mapping of System communication IEEE SOCC 2005 INTERNATIONAL

8. Outline • Introduction & Motivation • Existing Bus-based On-chip Communication Architectures • New Architecture Design • Test results • Conclusion IEEE SOCC 2005 INTERNATIONAL

9. Existing Communication Architectures • Evaluation of the Communication Architectures -- Design Complexity, Delay -- Control over the bus bandwidth fraction -- Communication latencies IEEE SOCC 2005 INTERNATIONAL

10. Static Priority Based Shared Bus IEEE SOCC 2005 INTERNATIONAL

11. TDMA Based Shared Bus IEEE SOCC 2005 INTERNATIONAL

12. TDMA Based Shared Bus IEEE SOCC 2005 INTERNATIONAL

13. LotteryBus Communication Architecture IEEE SOCC 2005 INTERNATIONAL

14. Lottery manager for static LOTTERYBUS architecture IEEE SOCC 2005 INTERNATIONAL

15. Advantages of LotteryBus IEEE SOCC 2005 INTERNATIONAL

16. Outline • Introduction & Motivation • Existing On-chip Communication Architectures • Proposed New Architecture Design • Test results • Conclusion IEEE SOCC 2005 INTERNATIONAL

17. Proposed Communication Architecture – Fraction Control • Every master core is assigned a bus access fraction, the higher the fraction, the higher the priority • the bus access will be decided by the Fraction Control bus arbitration rules statically or dynamically IEEE SOCC 2005 INTERNATIONAL

18. Proposed Communication Architecture – Fraction Control IEEE SOCC 2005 INTERNATIONAL

19. 2. Communication Protocol Design– Fraction Control • Static Fraction Control Bus: the assigned fractions are fixed during execution • Dynamic Fraction Control Bus: -- If any of the master core starves for bus access, it’s assigned fraction will be increased, and the difference will be borrowed from higher priority master cores temporarily. -- The borrowed part will be returned to the original owner when the situation has been changed. IEEE SOCC 2005 INTERNATIONAL

20. Communication Protocol Design– Fraction Control • Input: request[1..4], /* bus requests */ • fraction[1..4]; /* master’s fractions */ • t_finish[1..4]; /* transactions finished*/ • Output: grant[1..4]; /* bus grant signals */ • for i=1 to 4 do /*grant clear when task*/ • if (t_finish[i]==1) then grant[i]=0; /* is finished*/ • While (request<>0 and grant==0) • { if (request[i]==1 or 2 or 4 or 8) /*only one master*/ • then grant[i]=1; /*has bus request */ • elsefor i=1 to 4 do • if (no master’s fraction< assigned fraction) • then grant[i]=1; /*master i is the master • with highest priority */ • else if(only master i’s fraction<assigned fraction) • then grant[i]=1; • else grant[i]=1; /*master i is the master • with highest priority */ • } IEEE SOCC 2005 INTERNATIONAL

21. 2. Communication Protocol Design– Fraction Bus • Bus Arbitration Case 1: When only one master core is asking for bus access, the bus will be granted directly, no calculations needed ( LotteryBus, however, will still perform the computation—multiplication, random number generation and comparison) IEEE SOCC 2005 INTERNATIONAL

22. 2. Communication Protocol Design– Fraction Bus • Bus Arbitration Case 2: When more than one master cores are asking for bus access, and no master’s current bus fraction is lower than the assigned bus access fraction, the bus access is granted to the master with higher Priority( or with higher assigned Bus Access Fraction) IEEE SOCC 2005 INTERNATIONAL

23. 2. Communication Protocol Design– Fraction Bus • Bus Arbitration Case 3: When more than one master cores are asking for bus access, the bus will be granted to the master core with the current bus bandwidth fraction lower than the assigned bus access fraction (if more than one master satisfy this condition, bus access will be decided by their priority) IEEE SOCC 2005 INTERNATIONAL

24. Outline • Introduction & Motivation • Existing On-chip Communication Architectures • New Architecture Design • Test results • Conclusion IEEE SOCC 2005 INTERNATIONAL

25. Generic Test System • We implemented the priority Bus, LotteryBus, SFCB and DFCB architectures, and map the architectures onto • Xilinx Vertex2Pro FPGA. The targeting device is xc2vp2, package fg456. • Modelsim SE 5.8C and Xilinx ISE IEEE SOCC 2005 INTERNATIONAL

26. Generic Test System IEEE SOCC 2005 INTERNATIONAL

27. Generic Test System • Application: 8*8 matrix multiplication -- every master core performs computation for two rows of the result matrix (18 reads of 8 words input data, 16 writes of two words output data and 16*8 word multiplications and 16*7 additions for every master core) IEEE SOCC 2005 INTERNATIONAL

28. Generic Test System • Priority– MC1=4, MC2=3,MC3=2, MC4=1 ( 1-4, High to low) • Lottery– MC1=1, MC2=1, MC3=4, MC4=6 ( 1:1:4:6) • Fraction– MC1=8%, MC2=8%, MC3=32%, MC4=52% (1:1:4:6.5) IEEE SOCC 2005 INTERNATIONAL

29. Design Complexity, Speed and Bandwidth Fraction IEEE SOCC 2005 INTERNATIONAL

30. Generic Test System Communication latencies (clock cycles/ per word, including waiting time and transfer time) IEEE SOCC 2005 INTERNATIONAL

31. ATM Switch Architecture IEEE SOCC 2005 INTERNATIONAL

32. ATM Switch Architecture • (1) traffic through port 4 needs to pass through the switch with minimum latency, and • (2) ports 1,2,3 must share the bandwidth in the ratio1:1:4. IEEE SOCC 2005 INTERNATIONAL

33. ATM Switch Architecture • (1) static priority architecture, priorities were 4,3,2,1 • (2) Lottery Bus, lottery numbers were 1:1:4:6 • (3)(4) SFCB and DFCB, 15%:15%:60%:10%. IEEE SOCC 2005 INTERNATIONAL

34. ATM Switch Architecture IEEE SOCC 2005 INTERNATIONAL

35. Outline • Introduction & Motivation • Existing On-chip Communication Architectures • New Architecture Design • Test results • Conclusion IEEE SOCC 2005 INTERNATIONAL

36. Conclusion • Priority—Bad Bandwidth distribution control, significant communication latencies for lower priority components • LotteryBus– better bus bandwidth distribution control than Priority bus, (tickets ratio 1:1:4:6, result 1:1.5:3:4.2) with fair communication latencies IEEE SOCC 2005 INTERNATIONAL

37. Conclusion • SFCB&DFCB 1. Comparative bandwidth distribution; 2. SFCB has better bus bandwidth control (assigned ratio 1:1:4:6.5, result 1:1:3.8:5.8); 3. DFCB has more balanced bus bandwidth distribution which increases the usage of the system resources and the system efficiency. IEEE SOCC 2005 INTERNATIONAL

38. Thank you!! IEEE SOCC 2005 INTERNATIONAL