1 / 23

SRS News SRU Revision, New Hybrids, DTC, Firmware, …

SRS News SRU Revision, New Hybrids, DTC, Firmware, …. Sorin Martoiu, CERN PH/DT. Outline. SRU revision 2 (PCB produced, assembly) New Hybrids New APV Hybrids produced (micro HDMI connector) VFAT2 and BEETLE hybrids under design SRS Firmware Evolution New features for near-future upgrades

goodwinj
Download Presentation

SRS News SRU Revision, New Hybrids, DTC, Firmware, …

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. SRS NewsSRU Revision, New Hybrids, DTC, Firmware, … Sorin Martoiu, CERN PH/DT SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  2. Outline • SRU revision 2 (PCB produced, assembly) • New Hybrids • New APV Hybrids produced (micro HDMI connector) • VFAT2 and BEETLE hybrids under design • SRS Firmware Evolution • New features for near-future upgrades • New APV firmware options (Zero-suppression code) • Design of the DTC link • LVDS channel tests • Towards an industrial SRS design SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  3. SRU rev2 SRU revision 1 features: • 4 x SFP+ (GbE, ALICE DDL, ATLAS S-Link, …) • SO-DIMM DDR3 (2GB) • TTC • Remote configuration (BPI Flash) SRU revision 2 upgrades: • 10 GbE PHY • 3 x SFP+ (up to 5 Gbps each) • Jitter-cleaner PLL for TTCrx clock ( < 50 ps peak-to-peak jitter) SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  4. 3 x SFP+ 10 GbE New 10GbE PHY New PLL (TTC CLK) DDR3 SODIMM Virtex 6 FPGA SRU rev2 SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  5. New Hybrids • New APV Hybrid • VFAT2 Hybrid • BEETLE Hybrid New Micro HDMI connector • Initial production yield < 90% • Some simple assembly issues and some test samples included in the yield. • Final result may improve SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  6. New Hybrids • New APV Hybrid • VFAT2 Hybrid • BEETLE Hybrid • 2 hybrid versions (with or without discharge protection) • Power via detector PCB (option) • Signals via detector PCB (option for the short version only) • One hybrid per HDMI cable • Work in progress (layout finalization) SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  7. New Hybrids • New APV Hybrid • VFAT2 Hybrid • BEETLE Hybrid • Under design at Weizmann Institute, Israel • Comparator output OR/MUX via radtol CPLD • Master-slave versions for analog readout mode • Work in progress (layout finalization) SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  8. Firmware Evolution • Test modules • Used for QA tests in manufacture process • DTC Link • Protocol definition • Synch Module (clock synchronization of multiple FEC cards) • On-board clock (free running) • DTC clock (SRU clock) • Ethernet clock (TX clock of the Network Switch) • Design Partitioning (Xilinx tool migration) • Easy integration of new applications/front-ends • Partial reconfiguration of the application module (limited support for Virtex 5 family) SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  9. Firmware Evolution Voltage oC EEPROM Clock Unit Test & Init On-board clock Current DTC clock System SC Monitoring Ethernet clock SC BUS SC Core DTC Link App Slow Control Ethernet Core DAQ Readout Control FE Data path FE Card Interface Data Processor Packet Builder System Layer (Fixed partition) Application Layer (Reconfigurable partition*) * Xilinx dynamic reconfiguration support is limited for Virtex 5 FPGAs SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  10. APV Signal Processor 50kB Designed by Raffaele Giordano, INFN Napoli BYPASS 50kB Event Build 0 - 3 kB/ch - Frame Decode - Pedestal Corr. - Zero Suppress. 50kB 50kB SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  11. Clock phase calibration • Wrong clock-edge sampling; resync using the on-hybrid PLL25 chip SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  12. APV Frame Decoder Analogue data (128 channel samples) sync pulses headers SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  13. APV Zero Suppression Analogue data (128 channel samples) • Pedestal correction • Zero suppression (integral discrimination) • Thresholds are automatically calculated from noise data • User can read or write pedestal and noise data via slow-controls SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  14. DTC Links • SRU 40 x DTC links • 2 x LVDS TX (clock, trigger, control) • 2 x LVDS RX (data, trigger, control) • Physical Interface • LVDS buffers (< 2 Gbps, no signal conditioning) • CAT 5E/6/7 FTP SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  15. DTC LVDS Link Tests 100 MHz DDR PRBS pattern (400Mbps) 2.5 m 2.5 + 10 m 2.5 + 15 m 26 m SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  16. DTC LVDS Tests (Preliminary) 1Only one FEC card tested. Results may be different for a representative population; 2FPGA design limit 3Failed at 280 MHz. Safe value 260 MHz (1.04 Gbps; 0.8 Gbps effective) • 50 m DTC link not feasible • Signal conditioners might be an option • Data bandwidth higher than expected at moderate cable length ( > 1 Gbps) SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  17. Ch. request Flow control Framing Control Frame detection ctrl commas commas Latency correction High priority ch. Trigger/Busy/… 8b/10b 10b/8b Low priority ch. Data/Control DTC TX DTC RX DTC Protocol Proposal • Channel interleaving • Trigger, busy, … transmitted with high priority and guarantied fixed latency. • Data transmitted over regular (low priority) channel. • 8b/10b encoding • DC balance (improves channel performance) • Error detection • “Out-of-band” signaling (comma characters – synchronization, framing control, …) • 20% overhead • Versatile Design (Auto-negotiation, full control of slave DTC via SRU) SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  18. DTC Protocol Proposal SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  19. SRS in Industrial Standard AdvancedTCA • Discussions with EICSYS GmbH (Hamburg) studying the possibility to develop SRS systems in industrial standards (ATCA, mTCA, ..) • Full industrial certification (CE, mechanical, EMI, …) • Runtime reliability (>99.9% uptime) • System Management SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  20. Thank you! SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  21. Additional Slides SRS News, Sorin Martoiu, CERN 2012, 9th RD51 Collaboratin Meeting

  22. SRS ZS Data Format Data types and structures definition typedef unsigned char BYTE; // 8-bit word typedef unsigned int WORD32; // 32-bit word typedef unsigned short int WORD16; // 16-bit word typedef signed short int INT16; // 16-bit signed int struct APV_HEADER { BYTE APV_ID; // APV Identifier number on the FEC card (0 to 15) BYTE N_CHANNELS; // the number of channels which will be following the header BYTE N_SAMPLES; // the number of samples per channel BYTE ZS_ERROR; // Error code from the Zero Suppression Block, meaning have to be defined WORD16 FLAGS; // bit 0 : ‘0’ – Classic zero suppression, ‘1’ – Zero suppression with peak finding // bits 1 to 15 are still reserved for future use WORD32 RESERVED; // 32 bits reserved for future use }; struct CHAN_INFO { BYTE RESERVED; // 8-bits reserved for future use BYTE CHAN_ID; // Channel identifier, // APV physical channels are 0 to 127, // 128 could be used for the common mode average // 129 for error codes from the APV (pipeline address(8 bits) & error bit) INT16 CHANDATA[N_SAMPLES]; // 16 bit words, actual data will be 13-bits wide }; Author: Raffaele Giordano Ver. 0 25 Jan. 2012

  23. Read-out Sequence At each read-out from the ZS buffer for a given APV, the ZS will answer with this sequence. APV Header CHAN_INFO N_CHANNELS CHAN_INFO structures CHAN_INFO In classic zero suppression mode, the CHANDATA array contains the actualsamples. In peakfinding mode, the CHANDATA array hasalwaystwoelements: CHANDATA[0] = peakvalue CHANDATA[1] = peak time CHAN_INFO Author: Raffaele Giordano Ver. 0 25 Jan. 2012

More Related