A Skeleton NIOS II Project for the DE1 board :

1. A Skeleton NIOS II Project for the DE1 board : Hardware Specification, Software Design and Simulation Muthuswamy, Bharathwaj Milwaukee School of Engineering muthuswamy@msoe.edu September 2011

2. In this presentation, we will go through the steps required for setting up a NIOS II system on the DE1 board. Note that the process for creating a NIOS II system is clearly explained in the NIOS II Hardware Development Tutorial and NIOS II Software Developer's Handbook (May 2011), both available from Altera's website. However to make things interesting, we slightly modify the design steps in the two documents as we go through this presentation. The changes will be highlighted in bold red throughout the presentation. A summary of the changes is shown below: 1. We will use peripherals to communicate with two LED hex displays on the DE1 board. The Altera tutorial uses the NIOS to write to only eight LEDs or one hex display. 2. We will setup the design for ModelSim simulation. We will instantiate the NIOS processor using top level VHDL instead of block diagrams. We will create a blank software project instead of using a pre-defined project. Remember that all design files and tutorial documents are available on the Digital Systems Website. But you should go through the entire tutorial once so that you understand the main steps involved in creating a NIOS II system. This tutorial was designed on the Windows 7 version of the software, so some of the screens may slightly vary across different operating systems. The final block diagram of our design from the Quartus II RTL viewer is shown below, notice that the NIOS II software processor encapsulates the entire design. We have also shown a screenshot of the resource usage from the Quartus II synthesis reports. Caution: As your NIOS II designs increase in complexity, your synthesis times will increase substantially. For example, it takes 13 minutes on MSOE’s Windows 7 laptop to fully synthesize the design for this presentation. Hence it is highly recommended that you think through your designs before writing any hardware descriptions. If you keep re-synthesizing for small changes in your design, you will never finish the course project or any such realistic design projects.

3. NIOS II System Development Flow The NIOS II is a 32-bit little-endian RISC soft-processor from Altera. The overall block diagram of the flow is shown below.

4. Generating Hardware (Qsys) and Software (Software Build Tools or SBT for Eclipse) 1. Start NIOS II hardware development by selecting Tools->Qsys in Quartus 11.0, use Qsys to configure your NIOS II hardware 2. Once you finish adding the hardware, we will start NIOS II software development by running NIOS II SBT for Eclipse as administrator. Do not invoke SBT from within Quartus! Rather, right-click on the NIOS II SBT for Eclipse on your desktop (should be installed there by default) and then choose “Run as administrator”. We will only focus on downloading the .elf directly to the NIOS system

5. Step 1 : Generating Hardware using Qsys You need to complete the following steps to synthesize a minimal NIOS II system 1. Choose the Cyclone II device family (Project Settings tab) and set the clock frequency to 50 MHz (Clock Settings tab) 2. Processor systems require at least one memory (for data and instructions). We will use one 20 KB on-chip memory for both data and instructions. Refer to p. 1-12 in the NIOS II Hardware Development Tutorial on how to add on-chip memory. Result is shown below. Ignore the memory not connected error, we will fix this later.

6. 3. Now we will add the NIOS II processor, refer to p. 1-14 of the NIOS II Hardware Development Tutorial. Result is shown below. Note that we have highlighted the connections between the different peripherals. 4. Next we will add a JTAG UART module that will provide a convenient way to communicate with the host PC via the USB blaster download cable. The details are in p. 1-17 of the NIOS II Hardware Development Tutorial, the result of adding the peripheral is shown below.

7. 5. We will also add an interval timer that will serve a periodic system clock, the NIOS II HAL (Hardware Abstraction Layer) requires this timer. Refer to p. 1-18 of the NIOS II Hardware Development Tutorial, the result of adding the peripheral is shown below. 6. We MUST add a System ID peripheral that safeguards against accidentally downloading software compiled for a different NIOS II system. Note that SBT will not allow you to communicate with the NIOS II hardware without the system ID peripheral. Refer to p. 1-19 of the NIOS II Hardware Development Tutorial, the result of adding the peripheral is shown below.

8. 7. We will finally add a PIO (Programmable I/O) peripheral. Although this peripheral is optional, we will connect this PIO to the seven segment display and display the message “HI” via software. This will provide visual feedback that our processor system has not crashed. Refer to p. 1-20 of the NIOS II Hardware Development Tutorial, the result of adding the peripheral is shown below. Make sure that you double click on the led_pio and configure the bus width to be 16 instead of 8. This is because we are going to be interfacing to two HEX displays. Also, set the reset value to be 0x4040. This will display “00” on HEX1-HEX0. That way, we will know the processor is in reset state. 8. At this point we have added all the necessary hardware, now we will describe how the components interact to form the complete hardware system. This involves specifying base memory addresses for each slave component and assign interrupt request (IRQ) priorities for the JTAG UART and the interval timer. Note that the process of accessing peripherals via memory addressing is called memory-mapped I/O. Refer to p. 1-22 of the NIOS II Hardware Development Tutorial for details. Once you are done with this step, all errors in Qsys should have been resolved and we are ready for Qsys to generate VHDL. Also, make sure that the Generation Tab is configured for ModelSim simulation as shown below. I have used the project name “NiosDemo”. You can use any project name, just make sure that simulation and synthesis files are stored in separate directories. An important note, if you are using a UNIX based operating system, make sure that you enable en_US locale via a command prompt: $ sudo locale-gen en_US If you don't do this, Qsys will not generate hardware. This is a bug in Qsys that Altera should resolve in future Qsys versions.

9. 9. Now we will instantiate the Qsys system module in the Quartus II project, assign FPGA device and pin locations, compile the Quartus II project and verify timing. Do not close the Qsys window. Refer to p. 1-24 of the NIOS II Hardware Development Tutorial for instructions on how to complete system instantiation in Quartus II. Call your Quartus II project “NiosDemoInstance”. The hw_dev_tutorial.sdc file for timing analysis is available on the Digital Systems Website. Once you instantiate the project, create the top level entity as shown in the screenshot from a synthesis run below. Note that the instantiation template for the NIOS processor is available in Qsys. Check the HDL example tab. Remember to import pin assignments! Download the design to the DE1. The time limit for using the NIOS core is unlimited as long as the USB blaster cable is connected. But, do not remove the cable as this leads to unexpected issues with Eclipse. We will next program the design using SBT for Eclipse.

10. Step 2 : Generating Software using SBT for Eclipse The details on using SBT can be found in the NIOS II Hardware Development Tutorial, starting on p. 1-32. We will slightly deviate from the tutorial in the sense that we will create a blank project and then add the .C, .H files. First, start NIOS II SBT for Eclipse as administrator. Create a new workspace for this project and be sure to keep workspaces for different projects in different directories. Next, follow the tutorial but instead of creating the count_binary project, create a blank project named “display_hi”. Then download the display_hi.c and display_hi.h files from the Digital Systems Website to the display_hi folder under the software directory. Right-click on the display_hi folder under the Project Explorer in Eclipse and choose Refresh. Double-click on display_hi.c to open the file, the resulting Eclipse window is shown below. When you create a Run configuration to execute the ELF file on the board, you may get a timestamp mismatch error. You can safely ignore this error.

11. ModelSim simulation A functional simulation in ModelSim is easy to setup, refer to the tt_nios2_simulating.pdf available on the Digital Systems Website. The only change from the simulation pdf is that we will manually add the led_pio signal to the wave window. The complete simulation is shown below.

12. Concluding Tips Do not mix up project directories. Or you will spend 3 hours (like yours truly) before finally figuring out you were compiling the incorrect version of a .vhdl file. 2. Try to debug hardware and software separately. For example, test to make sure that you wired the LEDs and switches correctly to the processor pins. 3. I would highly recommend understanding how to use the command line tools for NIOS II interface as opposed to Eclipse. The Eclipse GUI is very buggy and unreliable. For information on how to use NIOS II command line tools, refer to the tt_nios2_command_line.pdf on the Digital Systems Website. 4. For interfacing to standard external peripherals (like the LCD display on the DE2 board) from the NIOS II, Altera provides a set of cores via the University Program. Search the Altera website to find the University Program executable and download+install the cores on your computer. 5. Browse through the files generated, especially the source generated by Eclipse. System.h under the BSP section has the memory mappings for all the hardware generated. A quick glance will help confirm that the correct hardware has been generated. 6. When using external memory, ALWAYS run a memtest first 7. Pay attention to the setup times, hold times etc. mentioned in the documentation. For example, the SD card interface specifies tSU and tCO times of 10 ns. If you don’t adhere to these specs. via the TimeQuest timing analyzer, there is a good chance for data corruption. 8. R.T.F.M. and K.I.S.S are your friends!