Training Scheme Analysis for Memristor-Based Neuromorphic Design

1. Training Scheme Analysis for Memristor-Based Neuromorphic Design • Miao Hu1, Hai Li1, Yiran Chen1, Qing Wu2 and Garrett S. Rose2 • Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, PA, USA 15261. • 2. Air Force Research Laboratory, Information Directorate, 525 Brooks Road, Rome, New York, USA 13441. Convergence Speed Analysis Simulation Results Abstract Memristor-based BSB Recall Circuit In this work, we propose a hardware realization of the Brain-State-in-a-Box (BSB) neural network model training algorithm. This method can be implemented as an analog/digital mixed-signal circuit to train memristor crossbar arrays within BSB circuits. The training effect is demonstrated through experimentation and the quality as an auto-associative memory is also analyzed and compared with software based training methods. The impacts of non-ideal device characteristics and fabrication defects in crossbar arrays are discussed. Our hardware architecture shows great potential for low power, high speed, small hardware size computations, and provides inherent security features. The training effect is achieved. An clear convergence gap can be observed between trained pattern and other untrained patterns. Physical constraints in hardware training Error correction rate. Limited data access: A crossbar array represents the terms in a weight matrix by analog states of memristors – memristance. Reading the exact memristance of the entire array is significantly costly in terms of design complexity as well as performance overhead. Limited accuracy of signal detection: The output signals of the memristor crossbar in analog format shall be used to control the training scheme. The accuracy in detecting these output signals affects the quality, speed, and cost of the overall training procedure. Non-ideal device characteristics: For example, the evolution of the memristance for actual memristive devices tends to be nonlinear. Therefore, applying the same excitation can result in different memristance change, depending on the state of memristor. Process variations and defects: Due to process variations, memristors in a crossbar array are not always the same. For example, the upper- and lower-bounds of memristance varies [16][17]. Moreover, “dead cells” stuck at high-resistance state (HRS) or low-resistance state (LRS) could exist. Embedded BSB Training Circuit Algorithm modification: Uniform size of domain of attraction. Table 1. Quality of domain of attraction. Memristor Theory STEP 1: Initializing the crossbar arrays. At the beginning of a training procedure, all memristance values in M1 and M2 are initialized to approximate the average of RL and RH. The initialization doesn’t have to be precisely accurate. Indeed, even when all the memristors are all at LRS or HRS, the crossbar arrays can still be successfully trained but it requires more time to reach convergence. STEP 4: Error detection. Since an input signal Vin(i) is ±0.1V, the preset threshold voltages can be used to compare Vout(i) and λ∙ Vin(i),. We employ four threshold voltages, including: Here, θrepresents the tolerable difference. In 2008, HP Lab demonstrated the first memristive device, in which the memristive effect was achieved by moving the doping front along a TiO2 thin-film. Figure (a) and (b) illustrate the conceptual view of the TiO2 thin-film memristor and the corresponding variable resistor model, which is equivalent to two serially-connected resistors. Here, RL (RH) is used to denote the low (high) resistance state (LRS and HRS). The overall resistance or memristance can be expressed as: where is the relative doping front position, which is the ratio of doping front position over the total thickness of the TiO2 thin-film. When the electrical excitation through a memristor is greater than the threshold voltage, the memristance changes (in training). Otherwise, a memristor behaves like a resistor. STEP 2: Selecting a prototype pattern  (k) Bn(k=1,…,m).Here, Bis the n-dimension binary space (1, 1). Assume a training set includes m prototype patterns and each pattern  (k)has the same probability to be chosen every time. Here, we use a counter ST to record the number of patterns that have passed training in sequence. When ST > 0, the corresponding patterns that passed training are excluded from the selection. STEP 5: Program memristor crossbar. Note that training the memristor crossbar array is conducted column by column. To train the jth column, the polarity and amplitude of the training pulse is determined by Diff(j). The training pulses are supplied on the rows of memristor crossbar arrays. The jth column is connected to ground and all the other columns are floating. For a column, the training pattern is either the current selected prototype pattern or the opposite pattern. Acknowledgement This material is based upon work supported by the National Science Foundation under Grant No. EECS-1311747, ECCS-1202225, and CNS-1253424. Received and cleared for public release by AFRL on May 1, 2012, case number 88ABW-2012-2568. Any opinions, findings and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of NSF, AFRL or its contractors. STEP 3: Sending  (k) to BSB recall circuit. We convert  (k)in binary space (1, 1) to a set of input voltages within the boundary (0.1V, 0.1V). These input signals are supplied to the two memristor crossbars simultaneously. The output signals can be obtained at the end of the BSB recall circuit. STEP 6: If training is completed?The counter ST increases by 1 if a prototype pattern goes through STEP 25 and reports no error without further tuning M1 and M2. Otherwise, ST is reset to 0 whenever an error is detected. Repeat STEP 25 until ST reaches m.