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Group: 17 Name: Shaun Prakash (1061107216) Jai Prakash (1061105253) Rajendran (1061105607)

Integrated VLSI Systems EEN4196 Title: 4-bit Parallel Full Adder. Group: 17 Name: Shaun Prakash (1061107216) Jai Prakash (1061105253) Rajendran (1061105607). Introduction Design Methodology Schematic Diagram Simulated Result Layout Conclusion. Contents. Introduction.

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Group: 17 Name: Shaun Prakash (1061107216) Jai Prakash (1061105253) Rajendran (1061105607)

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  1. Integrated VLSI Systems EEN4196 Title: 4-bit Parallel Full Adder Group: 17Name:Shaun Prakash (1061107216)Jai Prakash (1061105253)Rajendran (1061105607)

  2. Introduction Design Methodology Schematic Diagram Simulated Result Layout Conclusion Contents

  3. Introduction 4-bit Parallel Full Adder

  4. Introduction 4-bit Parallel Full Adder Binary Addition and Operation

  5. Design Methodology

  6. In our full adder design, we are using the 0.35 µm CMOS technology. So the length of the transistor we fixed to 0.35 µm. L = 0.35 µm The default ratio of W to L W/L = 3  So, we design the width of the NMOS 2.5 times its length WN = 0.35 µm x 3 = 1.05 µm As the width of the PMOS is 2 times the width of NMOS, hence WP = 1.05 µm x 2 = 2.1 µm Transistor Sizing

  7. Schematic Diagram Schematic Diagram of Full Adder

  8. Schematic Diagram Schematic Diagram of 4-bit Parallel Full Adder

  9. Output for First Block Simulation Result

  10. Output for Second Block Simulation Result

  11. Output for Third Block Simulated Result

  12. Output for Fourth Block Simulated Result

  13. Simulated Result Power Dissipation • As temperature increases, power dissipation increases

  14. Propagation Delay • Proportional • As the temperature increases, the propagation delay increases Due to degradation of carrier mobilities when the temperature is increased. Simulated Result

  15. Layout Layout of One Full-Adder Block

  16. Same transistor types are grouped together  less complex design. • To reduce the total size occupied.  reduce power consumption. • The rule of thumb technique reduce the collision between metal routings and to reduce the complexity during top-level design. Layout Technique

  17. Transistor count: 112 (28 per full adder circuit) • Layout area: 163.4µm x 227.1µm • Power dissipation (27oC): 5.0536mW Conclusion

  18. In conclusion, the schematic designed in this project is acceptable, at which the performance and delay is under reasonable range. The design can be considered as successful, due to the adequate precision and low power consumption. Future improvement on the current design is possible to achieve higher performance. Conclusion

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