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System Aspects of ADC Design

System Aspects of ADC Design. SHANTHI PAVAN Assistant Professor Department of Electrical Engineering Indian Institute of Technology, Madras. Prakash Easwaran, C Srinivasan Cosmic Circuits. 05/18/01 V4.3. A-to-D Converters Terminology & Architectures. 05/18/01 V4.3.

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System Aspects of ADC Design

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  1. System Aspects of ADC Design SHANTHI PAVAN Assistant Professor Department of Electrical Engineering Indian Institute of Technology, Madras Prakash Easwaran, C Srinivasan Cosmic Circuits 05/18/01 V4.3

  2. A-to-D Converters Terminology & Architectures 05/18/01 V4.3

  3. PRESENTATION OVERVIEW • ADC System Overview • ADC Metrics • Flash & Folding Converters • Two Step Flash Converters • Pipeline & Delta-Sigma ADCs • Power efficiency of ADCs • Conclusions

  4. A GENERIC MIXED-SIGNAL SYSTEM

  5. THE A-D CONVERSION PROCESS Anti-alias filter limits input bandwidth to fs/2

  6. ADC OPERATIONS : SAMPLING • Input typically stored as charge on a capacitor • Tracking bandwidth • Aperture • Hold pedestal

  7. QUANTIZER BASICS • Quant. error assumptions • uniformly distributed • uncorrelated with input ! • white !

  8. OFFSET ERROR Ideal • Benign when relative accuracy is desired - Cancelled digitally Actual

  9. GAIN ERROR Actual Ideal • Benign when relative accuracy is desired • Correct using AGC • in the analog/digital domains

  10. DIFFERENTIAL NONLINEARITY (DNL) • Nonmonotonicity & missing codes • Monotonic if |DNL| < D

  11. INTEGRAL NONLINEARITY (INL) • Measures deviation from a line • |INL| < 0.5 D sufficient condition for a monotonic characteristic

  12. DNL & INL REMARKS • DNL & INL should be measured with the best fit line for good repeatability • DNL - picture of local variations in quantizer thresholds • INL - picture of long range variations in quantizer thresholds

  13. DYNAMIC PERFORMANCE METRICS • Signal to Noise Ratio (SNR) • Signal to quantization noise • (6N + 1.76) dB for a sine wave • 1/2 the step size means ¼ the noise power • Signal to Noise + Distortion Ratio (SNDR) • Signal to everything else • Spurious Free Dynamic Range (SFDR) • Signal to the largest spectral spur • Effective Number of Bits (ENOB)

  14. Input Tone Quantization Noise SPURIOUS-FREE DYNAMIC RANGE

  15. HARMONIC DISTORTION Distortion is related to INL

  16. SFDR DEPENDENCE ON “N” Amplitude is D Frequency ~ f Amplitude is D/2 Frequency ~ 2f ¼ the power over twice as many harmonics Peak harmonic goes down by ¼ ½ = 9 dB SFDR ~ 9N dB

  17. FLASH A-D CONVERSION • (+) Parallel technique - low latency • (+) References – resistor ladder • (-) Complexity - O(2N) • (-) Excessive power/area for N > 6

  18. THE CLOCK SKEW ISSUE • Sampling is distributed • Problem : Clock skew causes different comparators to sample inputs at different instances • Result : Poor performance at high input frequencies • Solution : Make all comparator inputs see “held” inputs

  19. PRACTICAL FLASH ADC • T/H for good dynamic performance. • Offset correction in comparators.

  20. BACKEND LOGIC

  21. THE FOLDING ADC PRINCIPLE • Motivation : Reduce latches & back end logic

  22. WHITHER FLASH & FOLDING ? • Disk drive read-channels • Low precision (6 bits) • Very high speed (Gbps) • Need very low latency (for timing recovery)

  23. TWO STEP FLASH ADC • Motivation: • Reduce number of comparators in a flash ADC • Idea: • In a flash ADC, only comparators “near” the input give useful information • Use a coarse ADC to estimate where the signal is, then use a fine ADC placed “around” the coarse estimate for better accuracy

  24. TWO STEP FLASH ADC Number of comparators : (2Nc + 2Nf – 2) Resolution Nc + Nf bits ADCs & DAC must be good to (Nc + Nf) bits

  25. Code : -2 -1 0 1 Slope = 1 ADC thresholds RESIDUE PLOT : A CLOSER LOOK

  26. Code : -2 -1 0 1 DAC LSB RESIDUE PLOT : A CLOSER LOOK

  27. Fine ADC overload ! Fine ADC Range ISSUE : ADC THRESHOLD OFFSET

  28. ADC THRESHOLD OFFSET : FIX Extend the range of fine ADC by adding extra levels Redundancy in fine ADC relaxes coarse ADC errors Often called “Digital Error Correction”

  29. DAC level error Slope = 1 Fine ADC range not exercised ISSUE : DAC INACCURACY DAC level too small : Missing codes DAC level too large : Non-monotonicity

  30. TWO-STEP FLASH SUMMARY • Example : • 10-bit flash needs 1023 comparators • (5 + 5) bit 2-step flash needs only 62 comparators • Lower hardware compared to a flash • More latency (2 conversions, pipelined) • Used for ~8-10 bit resolutions • Coarse ADC resolution can be poor if extra levels are used in the fine ADC • DAC must be accurate to the resolution of the entire ADC

  31. IMPROVED TWO-STEP FLASH ADC • The fine ADC operates on a small input • Offset requirements for the fine ADC can be relaxed if the input signal swing was larger • Amplify the input to the fine ADC

  32. PIPELINE ADC PRINCIPLE Recursive implementation of the fine ADC

  33. STAGE 1 STAGE 2 PIPELINE ADC PRINCIPLE • Nc bits per stage • Issue with ADC threshold error - Digital error correction • DAC & Interstage amplifier implemented with switch-capacitor circuitry

  34. OVERSAMPLING A-D CONVERSION Nyquist rate ADC Signal Oversampling ADC Quantization Noise

  35. OVERSAMPLING & NOISE SHAPING IDEA Quantization noise is pushed out of the signal band Digital filter required to eliminate out of band noise Very high SQNR possible with a poor quantizer Also referred to as SD ADCs

  36. SD MODULATOR BLOCK DIAGRAM Discrete time input & output Quantization modeled as additive noise

  37. Signal Transfer Fn. (STF) Noise Transfer Fn. (NTF) SD MODULATOR BLOCK DIAGRAM Make L(z) large in the signal band

  38. DELTA-SIGMA WAVEFORM EXAMPLE Analog Input Quantizer Output

  39. Signal Tone Signal Bandwidth Shaped Quantization Noise SD OUTPUT SPECTRUM

  40. OTHER LOW SPEED ARCHITECTURES • Algorithmic ADCs • Reuse a single stage of the pipeline • Successive Approximation ADCs • Dual-slope ADCs

  41. HIGH SPEED : “SYSTEM” IDEAS • Time – interleaving multiple ADCs • N slow converters to get one fast ADC • Sample and hold of each converter must be good up to fs/2 • Gain & Offset mismatch • N times speed for N times power

  42. ADC FIGURE OF MERIT • FOM Units : Joules per level resolved • Small FOM means more power efficiency • Higher speed – more power • Higher resolution – more power • ENOB : Effective number of bits for a Nyquist input

  43. FIGURE OF MERIT : COMMENTS • For the same ADC spec, FOM usually improves with technology (& skill of the designer !) • Ponder this : If “X” can design a 10-bit 500 Msps ADC in a certain process with 400 mW, does this mean that he/she can design a 10-bit, 1Gsps ADC with 800 mW ?

  44. POWER EFFICIENCY OF ADCs • Flash ADCs are least efficient • But unavoidable when latency cannot be tolerated • Pipelines more efficient than a flash • Reduced hardware at the expense of latency • Delta-Sigma more efficient than a pipeline • but only suitable for low bandwidth signals

  45. REFERENCES • M. Gustavsson, J. Wikner & N. Tan, “CMOS Data Converters for Communications”, Kluwer, 2000 • R. van de Plassche, “Integrated Analog-to-Digital & Digital-to-Analog Converters”, Kluwer, 1994 • R. Schreier, S. Norsworthy & G. Temes, “ Delta-Sigma Data Converters – Principles, Design & Applications”, Wiley, 1998

  46. A-to-D Converters Specifications from System Aspects 05/18/01 V4.3

  47. ADC Parameters • Sampling Frequency • Resolution • SFDR • Input Bandwidth • Latency

  48. System Aspects… • Signal Bandwidth • System SNR requirements • Signal characteristics • Dynamic Range • Interferers present • Single/Multi Carrier

  49. ADC requirements derived from Strengths of the Signal and interferers. Typical Real world signals Blocker -14dBm Weak Signal -40dBm -104dBm -114dBm Noise

  50. Sampling Frequency

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