Outline 3DIT improves MAPS performances

1. 3D CMOS monolithic 3-bit resolution pixel sensor with fast digital pipelined readoutOlavTorheim, Yunan Fu, Christine Hu-Guo, Yann Hu, Marc Winteron behalf of IPHC (Strasbourg) Outline • 3DIT improves MAPS performances • A 12 µm pitch pixel CMOS MAPS for the ILC vertex detector using 3DIT • 3D rolling shutter CMOS MAPS with fast digital pipelined readout • Analog tier: sensor, preamplifier and pixel-level ADC • Digital tier : SRAMs and data sparsification circuitry • Conclusions

2. Digital Analog ~ 50 µm Sensor Using 3DIT to improve MAPS performances • 3DIT are expected to be particularly beneficial for MAPS : • Combine different fabrication processes •  Split charge collection and signal processing functionalities •  Use best suited technology for each tier : • Tier-1: charge collection system  Thin epitaxial charge collection layer X0  • Tier-2: analogue signal processing Low Ileak, process, N metal layers shields from digital. • Tier-3: digital signal processing & data transmission • Resorb most limitations specific to 2D MAPS • Dead surface  • Power consumption • Readout speed • … • 2009: run in Chartered/Tezzaron technology • 3D consortium: coordinated by Fermilab Olav.torheim@ires.in2p3.fr

3. Tier 1 Tier 2 Acquisition Readout A B Detection diode or Q injection Amplifier Amp.+Shaper Discriminator Hit identification 5 bits (7) time stamp 2nd hit flag Readout ~1 ms + ~200 ms ~1 ms 24 µm TS & R.O. ASD 12 µm 12 µm Detection diode & Amp A 12 µm pitch CMOS MAPS in 3DIT for the ILC vertex detector • Delayed R.O. architecture for the ILC Vertex Detector (designed & submitted) • Trial 3D architecture based on small pixel pitch, motivated by : • Single point resolution < 3 μm with binary output • Probability of > 1 hit per train per pixel << 10 % • 12 μm pitch : • sp ~ 2.5 μm • Probability of > 1 hit/train/pixel < 5 % • 3D 2-tier process • Tier-1: A: sensing diode & amplifier, B: shaper & discriminator • Tier-2: time stamp (5 bits) + overflow bit & delayed readout  Architecture prepares for 3-Tier perspectives : 12 µm • Tier-1: CMOS process adapted to charge collection • Tier-2: CMOS process adapted to analogue & mixed signal processing • Tier-3: digital process (<< 100 nm ?) sp : ~ 2.5 μm Tint : ~ 31 µs Pow : ~ 3.47 W/cm2 (instantaneous power) 

4. Delay+SRAMs + Sparsification Detection diode+Amplifier +Pixel-level ADC ~ 25 µm 3D Rolling Shutter MAPS with fast pipelined digital readout • 3D MAPS with fast pipelined digital readoutaiming to improve spatial resolution and time resolution and to minimize power consumption (R&D in progress) • Subdivide sensitive area in ”small” matrices running individually in rolling shutter mode • Adapt the number of rows to required frame readout time  few µs r.o. time may be reached • Design in ~ 25 µm²: • Tier 1: Sensor & preamplifier + 3-bit pixel-level ADC (LSB ~RMS noise,15~20 e-) • Tier 2: SRAMs + Fast pipeline readout circuitry with data sparsification sp < 2.5 μmTint. ~ 7 µs Pow ~ 0.73W/cm2 (compromise of time res. and power) 

5. Track 3D Rolling Shutter Mode Digital Pixel Sensor Circuitry • Block diagram of the 3D integrated Rolling Shutter Binary Pixel (RSBPix) architecture with in-pixel amplification, double sampling, digitization and in-pixel digital circuitry. Feedback Analog Tier # Digital Tier # Vclp SF Clamp soff < 15 mV Vdd Vref Discrimination Preamp CS n+ MOSCAP Auto-zeroed N-well MiMCAP Comparator P-epi Chip-level analog ramp generator P-sub Auto-zeroed Track Chip-level Counter SRAM Vref S ~ 50 MHz • Negative feedback Stabilizes the operating point of the amplifier and robust against process mismatches • In-Pixel offset-compensated Multi-Stage Amplifier High gain, low offset voltage • Auto-zeroed comparator Low power, low offset voltage • Digital front-end Fast pipeline digital readout, data sparsification Digital Front-end (data sparsification) Digital output / X.Y Address

6. Phase1 Phase2 ( upper half ) Token ( upper half ) Rolling shutter Sub-array 1 Sub-array 1 ( lower half ) ( lower half ) Rolling shutter Token Row buffers Row buffers ( upper half ) Token ( upper half ) Rolling shutter Sub-array n Sub-array n ( lower half ) ( lower half ) Rolling shutter Token Token-compliant rolling shutter mode • Token-compliant rolling shutter mode the tokens must be injected into the upper half while hits are injected into the lower half, and vice versa: • Time resolution = TPhase1 + TPhase2 • Parallel data sparsification  Time resolution  Tint ~ 7 µs (adjustable) • “M” rows in each sub-array  M = Tint / (TA-to-D + TRESET) • Row buffers  Store the information of the hits in each row

7. Cell 1 Cell 0 Cell (M-1) Cell M NAND NAND NOR NOR Token_in Token_in Token_in Token_in VDD 1 0 0 3-bit data 3-bit data 1 A 3-bit data 3-bit data B B Logic A Logic B A Logic A Logic B Enable Enable Enable Enable 000 111 011 000 Reset Reset Token_CLK Token_CLK Reset Reset Token_CLK Token_CLK Token_in Token_CLK A Reset Enable 3-bit data Token_in Logic A Q Q D D Q Q Details of the Digital Front-end • A token passes through a chain of intertwined NAND and NOR digital pixel cells  To minimize delay time of token passing • “Enable” signal  Select signal for placing pixel address and 4-bit ADC value at shared row bus • Row buffers (Hits counter + shift registers) successively store hit information placed at row bus. 0 Token_in Token_CLK B Reset Enable 3-bit data Token_in Logic B

8. 3 Hits Buffer N-2 (Cell 511) Buffer N-1 (Cell 2) Buffer N (Cell 1) …. …. Cell 1 Hits counter Buffer 1 Row0 Cell511 Cell 0 Cell 1 Cell 2 Cell510 Token 2 Hits Buffer N-1 (Cell 511) Buffer N (Cell 0) …. …. Cell 0 Cell 1 Hits counter Buffer 1 Cell511 Row1 Cell 2 Cell510 Buffer N-2 .… .… .… Token 1 Hit Buffer N (Cell 510) …. …. Cell 0 Cell 1 Hits counter Buffer 1 Cell510 Cell511 Buffer N-1 Cell 2 Buffer N-2 RowM Token Row buffers • For every token clock cycle, the content on the line data bus is stored into the leftmost buffers, with the content of all the buffers being shifted from one buffer to the next, A hits counter increments the number of valid hits as long as the token injected into the row has not been returned. • Number of buffers must be adopted to hit density of experiment: • Low value of the background ( 3 hits/ cm2 / BX) , cluster multiplicity 6 “N” Buffers = 18 • High value of the background (15 hits/ cm2 / BX), cluster multiplicity 6  “N” Buffers = 30

9. Phase2 Phase1 read write Row 0 Row 0 Token Rolling shutter Row 1 Row 1 Row 2 Row 2 FSM FSM ( upper half ) ( upper half ) Row M Row M Row buffers Sub-array 1 Sub-array 1 Row buffers Mux Mux Row 0 Row 0 FIFO FIFO Row 1 ( lower half ) Row 1 ( lower half ) Rolling shutter Token Row 2 Row 2 Row M Row M 3-bit digital data X / Y address 3-bit digital data X / Y address read write Pipeline readout mode • Pipelined readout of Row buffers The row buffers in upper half are operated in pipelined scan mode while new hits are injected into the buffers of lower half, and vice versa: • Finite State Machine (FSM)  Reads content of each line before advancing the pipeline. • Due to pipelined operation, no upper limit on hits per line (like in MIMOSA26), only upper limit on hits per frame (dependent on FSM operating frequency).

10. Binary discriminated pixels / distributed hit pattern encoding • Patterns of hits in each line coded as states • Similar to MIMOSA26 but... • Algorithm moved from periphery and distributed into individual pixels. •  Higher time resolution. •  Covers higher hit density.

11. Distributed hit pattern encoding • State encoding logic must be minimized in order to fit into each pixel cell: • State encoding implemented as priority encoder • Simplified logic for nonredundant state identification

12. Conclusion and perspectives • A 12 µm pitch pixel 3D 2-tier CMOS MAPS with delayed and full serial readout architecture has been designed and being fabricated. • Sensor, front-end electronics and 5-bit TDC (Tint=31µs). • Full serial read-out speed : ~100 MHz. But in order to further improve the single point resolution, time resolution (< 10 us) and save power consumption: • A new architecture of 3D rolling shutter CMOS MAPS with fast pipelined digital readout is proposed: • Tier 1 : Sensor & preamplifier + 3-bit pixel-level ADC (LSB ~RMS noise,15~20 e-) • Tier 2: SRAMs + Fast pipeline readout circuitry with data sparsification