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Digital Fields Board (DFB) Critical Design Review Aref Nammari LASP

Digital Fields Board (DFB) Critical Design Review Aref Nammari LASP University of Colorado - Boulder. Requirements & Specs. Requirements & Specs. EFI REQUIREMENTS. Requirements & Specs. SCM REQUIREMENTS. IDPU Requirements. IDPU REQUIREMENTS. MASS Power Requirements.

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Digital Fields Board (DFB) Critical Design Review Aref Nammari LASP

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  1. Digital Fields Board (DFB) • Critical Design Review • Aref Nammari • LASP • University of Colorado - Boulder

  2. Requirements & Specs Requirements & Specs • EFI REQUIREMENTS

  3. Requirements & Specs • SCM REQUIREMENTS

  4. IDPU Requirements • IDPU REQUIREMENTS

  5. MASS Power Requirements • MASS POWER REQUIREMENTS

  6. Parts Requirements • Parts requirements

  7. Block Diagram

  8. Electrical Diagram Electrical Diagram Science Goal: Linear Phase—Bessel Filter 4KHz corner frequency 12dB attenuation at 8KHz CMRR(DC diff. Amp) 80dB EFI Filter

  9. EFI Filter Simulation Frequency Response—Amplitude and Phase

  10. EFI Filter Simulation Phase Delay

  11. Monte Carlo Analysis EFI Filter Gain Resistor Tolerance 1% TCR 50ppm/oC Capacitor Tolerance 1% TCR 30ppm /oC Temp: 27oC Mean 3dB frequency: 4111Hz Sigma: 32.47 10th %tile: 4067Hz 90th %tile: 4153Hz

  12. Monte Carlo Analysis EFI Filter Gain Resistor Tolerance 1% TCR 50ppm/oC Capacitor Tolerance 1% TCR 30ppm /oC Temp: -40oC Mean 3dB frequency: 4133Hz Sigma: 32.71 10th %tile: 4089Hz 90th %tile: 4175Hz

  13. Monte Carlo Analysis EFI Filter Gain Resistor Tolerance 1% TCR 50ppm/oC Capacitor Tolerance 1% TCR 30ppm /oC Temp: 50oC Mean 3dB frequency: 4103Hz Sigma: 32.4 10th %tile: 4059Hz 90th %tile: 4186Hz

  14. Monte Carlo Analysis EFI Filter Group Delay Filter remains of Bessel Type as components change within their tolerance value and over temperature

  15. 3dB Frequency -40oC 27oC 50oC Maximum 4231kHz 4194kHz 4182kHz Nominal 4147kHz 4111kHz 4099kHz Minimum 4066kHz 4030kHz 4018kHz Monte Carlo Analysis EFI Filter Summery 3dB frequency is not significantly affected by temperature or by component variation within the Specified tolerances. The table below is a summery of the worse case analysis performed at different Temperatures.

  16. Measured DFB_BB EFI Filter Gain Measured DFB (breadboard) EFI Filter Gain—V1 through V6 (single ended channels). Measured 3dB frequency is 4kHz with 12.8dB attenuation at 8KHz.

  17. Measured DFB_BB EFI Filter Phase Response

  18. Monte Carlo Analysis-DC Diff. Amp.CMRR

  19. Measured CMRR—DFB breadboard DFB-BB used .1% resistors no particular matching of resistors was done. Flight will use resistor divider network with .01% ratio tracking.

  20. EFI AC coupled differential channels EFI AC Coupled differential

  21. Simulation Results Frequency Response—AC coupled diff. EFI

  22. Measured DFB Dif. AC Filter Gain

  23. SCM Filter-Electrical Diagram

  24. Simulation Results

  25. Measured SCM Filter Gain -3dB frequency is 4.3KHz

  26. Measured SCM Filter Phase Response

  27. Monte Carlo Analysis Resistor Tolerance 1% TCR 50ppm/oC Capacitor Tolerance 1% TCR 30ppm /oC Temp: 27oC Mean 3dB frequency: 4299Hz Sigma: 21.05 10th %tile: 427Hz 90th %tile: 4327Hz

  28. CMRR SCM Filter No requirements were made as to CMRR. With 1% components the expected CMRR is 43dB. The CMRR could be improved by using better tolerance components.

  29. Measured CMRR—DFB Breadboard

  30. HF Channel--LogRMS HF Channel Band-Pass Filter 100kHz to 500KHz

  31. HF Channel--LogRMS LogRMS—Successive Detection Stage

  32. Measured Performance-DFB breadboard -3dB frequencies about 80KHz and 540KHz

  33. Measured Performance-DFB breadboard

  34. Measured Performance-DFB breadboard

  35. Mux Cross Talk Input signal sine wave at 100Hz. FFT yields about 70dB voltage magnitude at fundamentalfrequency

  36. Mux Cross Talk Adjacent mux channel shorted. FFT yields about -12dB voltage magnitude at fundamentalfrequency

  37. ADC NOISE

  38. Layout—Top Side

  39. Layout—Bottom Side

  40. Mechanical & Thermal Thermal

  41. Digital Fields Board FPGA (DFB FPGA) • Critical Design Review • Chris Cully and Ken Stevens • LASP • University of Colorado - Boulder

  42. DFB FPGA Data Flow

  43. Typical DFB Output Slow Survey

  44. Typical DFB Output Fast Survey = Slow Survey +

  45. Typical DFB Output Particle Burst = Fast Survey +

  46. Typical DFB Output Wave Burst = Particle Burst +

  47. DFB FPGA Conceptual Design DSP functions are performed using an application specific processor architecture with multiple processing elements that are optimized for their specific task(s).

  48. ADC Time Slot Assignment Sample timing and order is deterministic regardless of mode.

  49. Filter Banks Low pass section Bandpass section 8 kS/s + - Shift Z-3 7-tap FIR filter 2-4 kHz Averager 4 kS/s 2:1 Decimating FIR filter (3-tap) + - Shift Z-3 7-tap FIR filter 1-2 kHz Averager 2 kS/s 2:1 Decimating FIR filter (3-tap) (9 more banks) (9 more banks) + - Shift Z-3 7-tap FIR filter 1-2 Hz Averager 2 S/s 2:1 Decimating FIR filter (3-tap)

  50. Filter Banks

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