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RBSP EFW Digital Fields Board FPGA

RBSP EFW Digital Fields Board FPGA. Ken Stevens Laboratory for Atmospheric and Space Physics University of Colorado at Boulder. DFB Block Diagram. EFW – DFB Subsystem Performance Requirements. EFW – DFB Subsystem Performance Requirements. DFB FPGA: Overview.

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RBSP EFW Digital Fields Board FPGA

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  1. RBSP EFW Digital Fields Board FPGA Ken Stevens Laboratory for Atmospheric and Space Physics University of Colorado at Boulder EFW INST+SOC PDR

  2. DFB Block Diagram EFW INST+SOC PDR

  3. EFW – DFBSubsystem Performance Requirements EFW INST+SOC PDR

  4. EFW – DFB Subsystem Performance Requirements EFW INST+SOC PDR

  5. DFB FPGA: Overview • The DFB FPGA controls acquisition of the analog signals and converts them to a database of signals at various rates for further processing: • Analog to Digital Conversion • 16-bit resolution • 16.384ks/s (214) sample rate • Cross-strapped ADCs for limited redundancy • Field Alignment • Rotates E and SCM values into the coordinate system of the DC magnetic field • Digital Filtering • Multi-tap FIR low-pass filter that creates output rates from 1x sampling rate down to 1/(212)x sampling rate • Band-pass filter taps available for trigger value calculations EFW INST+SOC PDR

  6. DFB FPGA: Overview (cont) • The DFB FPGA generates the following types of data from the digital samples: • Trigger Data: • pseudo-power in 7 or 13 frequency bands • Any two EDC, EAC, or SCM values • Time Series (Waveform) Data: • Reporting rates from 4s/s – 16Ks/s: • V1-V6, V1AC-V6AC, E12DC-E56DC, E12AC-E56AC, FM1-FM3, SCM1-SCM3 • Spectra Data: • 2048-point FFT with selectable frequency binning and time averaging • Any eight signals except V1-V6 • Cross Spectral Data: • Selectable frequency binning and time averaging • Any four pairs from spectra data • Solitary Wave Detector Data: • Counts peaks and bins them according to magnitude • E12AC or E34AC EFW INST+SOC PDR Magnetometer Booms

  7. DFB FPGA: Implementation Approach • General Approach • Using an FPGA-based implementation allows hardware to be tailored to the mission requirements • Lower power than an equivalent processor based DSP design • Heritage from THEMIS • LTC1604 ADC and ADC support circuitry • Digital Signal Processing algorithms • Backplane interface protocols • Changes and Improvements • Higher sample rates (16ks/s) • Addition of onboard Cross Spectral Analysis and Solitary Wave Detection • Use of a single RTAX2000 FPGA instead of three SX72 FPGAs • Rewrite of FPGA VHDL code • Higher performance implementation of DSP algorithms • Utilization of RTAX internal RAM to improve data flow and performance • Parameterization of all modules to accommodate unforeseen design changes • Standardization of all internal interconnect buses to Wishbone architecture EFW INST+SOC PDR

  8. DFB FPGA: Top-level Block Diagram Backplane Interface Analog Muxes and ADCs SRAM EFW INST+SOC PDR

  9. DFB FPGA: Top-level Block Diagram Backplane Interface Analog Muxes and ADCs SRAM EFW INST+SOC PDR

  10. DFB FPGA: Command Processor • Decodes backplane protocol: • ‘1’ start bit • 8-bit command ID • 16-bit command data field • odd parity bit • ‘0’ stop bit • Performs command translation to create appropriate register read/writes from/to sub-modules. EFW INST+SOC PDR

  11. DFB FPGA: Data Processor • Assigns APIDs • Encodes ALU data products for backplane transport to the DCB using a synchronous UART interface: • ‘1’ start bit • 8-bit APID • 16-bit data field • odd parity bit • ‘0’ stop bit EFW INST+SOC PDR

  12. DFB FPGA: Top-level Block Diagram Backplane Interface Analog Muxes and ADCs SRAM EFW INST+SOC PDR

  13. DFB FPGA: Field Alignment Flow Diagram E12,34,56 B (from FGM) Adjust Gains, Offsets Offsets 5-minute lowpass filter to find offsets Adjust gain/offset Rotation matrix Gains Offsets (from ground) Rotate to E system (gains included) Adjust gain/offset Interpolate Rotate E, B simultaneously in the xy plane until Bx = 0. Perform rotations using CORDIC Rotate E, B simultaneously in the xz plane until Bz = 0. E_perp = Ey/1.646 E_par = Ex/1.6462 EFW INST+SOC PDR

  14. DFB FPGA: Digital Filters • Uses a cascading filter algorithm that allows generation of both low-pass and band-pass outputs. • Each filter bank requires about the same processing as 2 comparable filters (e.g. 5th order Bessel). • Since quantities are typically filtered to so many different rates, and since some quantities require a filter bank anyway, this approach saves complexity and power. • -3dB point = 0.6 fNyquist • Power at fNyquist= -12 dB • Rolloff ~ 25 dB/octave • No phase shift EFW INST+SOC PDR

  15. DFB FPGA: Digital Filters Diagram Low pass section Bandpass section 8 kS/s + - Shift Z-3 7-tap FIR filter 2-4 kHz Averager 4 kS/s 2:1 Decimating FIR filter (3-tap) + - Shift Z-3 7-tap FIR filter 1-2 kHz Averager 2 kS/s 2:1 Decimating FIR filter (3-tap) (9 more banks) (9 more banks) + - Shift Z-3 7-tap FIR filter 1-2 Hz Averager 2 S/s 2:1 Decimating FIR filter (3-tap) EFW INST+SOC PDR

  16. DFB FPGA: Top-level Block Diagram Backplane Interface Analog Muxes and ADCs SRAM EFW INST+SOC PDR

  17. DFB FPGA: Triggers • Selects appropriate band-pass filter value from the digital filters output • The power in a particular band is approximated by averaging the absolute value • The results are used mainly in triggering algorithms EFW INST+SOC PDR

  18. DFB FPGA: Waveforms • Selects appropriate low-pass filter values from the digital filters outputs • For each waveform output that is configured to use the low-pass filter value, the waveform player passes the value along to the data player along with a unique identifier EFW INST+SOC PDR

  19. DFB FPGA: Digital Filters Low-pass and Band-pass Response Curves EFW INST+SOC PDR

  20. DFB FPGA: Waveform Data Path Backplane Interface Analog Muxes and ADCs SRAM EFW INST+SOC PDR

  21. DFB FPGA: Spectra • Radix-2 Decimation in Frequency Algorithm • Sine/Cosine values are calculated in the FPGA using CORDIC • Eliminating read from sine table reduces RAM bandwidth • Simplifies the hardware and software design by eliminating the need for non-volatile memory or sine-table uploads EFW INST+SOC PDR

  22. DFB FPGA: Cross-Spectra • Sub-module located in the Arithmetic Logic Unit • Interfaces with the rest of the system using standard Wishbone interface • Currently in the definition/development phase EFW INST+SOC PDR

  23. DFB FPGA: Solitary Wave Detector • Sub-module located in the Arithmetic Logic Unit • Interfaces with the rest of the system using standard Wishbone interface • Currently in the definition/development phase EFW INST+SOC PDR

  24. DFB FPGA: Key Implementation Guidelines • Specification • Digital Fields Board Specification (RBSP_EFW_DFB_001A_SPEC Rev A) • Digital Fields Board FPGA Specification – In Progress • Coding Standards • LASP FPGA Design Guide (currently under development) • NASA 500-PG-8700.2.7 • Actel HDL coding Style Guide • Single clock domain • Fully Synchronous Design • Power-on reset is asynchronously applied, synchronously cleared • Scripts used for running simulations and builds to ensure consistency • Version Control • All source code, design documents, and test files are version controlled using Subversion • Major releases are archived in Agile CM system EFW INST+SOC PDR

  25. DFB FPGA: Resource Tracking • This is the top-level page of a more detailed worksheet that tracks the logic resources of all sub-modules • Numbers are preliminary for all functions • Estimates will be updated monthly as the design progresses EFW INST+SOC PDR

  26. DFB FPGA: Verification Plan • Extensive Behavioral Simulation of all logic • Test stimulus created with IDL • IDL generated data used as the input for the VHDL testbenches • IDL verification of data output from FPGA • Static timing analysis • Limited post place and route simulation • Design is too complex for full regression test of post place and route back annotated design • Extensive lab testing • Test data from the lab will be captured on a PC and compared to IDL models of the algorithms • This approach was very successful for THEMIS verification EFW INST+SOC PDR

  27. DFB FPGA: Initial ETU Functionality • Reprogrammable ProASIC 3E (A3PE1500) • Register read/writes • All analog channels supported • ADC sampling of all channels • Generation of waveform (time series) packets with real data • No field alignment, spectra/cross-spectra or solitary waveform detection processing • Functionality will increase with incremental FPGA releases after delivery of initial ETU EFW INST+SOC PDR

  28. DFB FPGA: Current Status & Next Steps • Current Status • Analog to Digital Converter Interface – Complete • Digital Filters – Complete • Waveform Player – Complete • Top-level Logic – Complete • Next Steps • Command Controller • Data Processor • Top-level simulation • FPGA load for initial board bring-up to pass waveforms through the system EFW INST+SOC PDR

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