K-Maps, Multi-level Circuits, Time Response

1. K-Maps, Multi-level Circuits, Time Response • Today: • Reminder: Test #1, Thu 7-9pm • First Hour: K-map example, espresso • Section 2.3 of Katz’s Textbook • In-class Activity #1 • Second Hour: Multi-Level Logic, All-NAND/NOR Circuits, Time Response • Section 3.1 of Katz’s Textbook • In-class Activity #2

2. A graphical way to express a truth table Highlights opportunities to apply the uniting theorem (ABX + ABX’ = AB(X+X’) = AB) with up to 4 variables AB CD 00 01 11 10 00 01 11 10 Recap: K-maps A donut-like representation! 1 1 1

3. A graphical way to express a truth table Highlights opportunities to apply the uniting theorem (ABX + ABX’ = AB(X+X’) = AB) with up to 4 variables AB CD 00 01 11 10 00 01 11 10 Recap: K-maps The “Boolean Lasso” expresses the uniting theorem 1 1 1 Remember: diagonally-adjacent terms cannot be united

4. A graphical way to express a truth table Highlights opportunities to apply the uniting theorem (ABX + ABX’ = AB(X+X’) = AB) with up to 4 variables AB CD 00 01 11 10 00 01 11 10 Recap: K-maps The bigger the lasso, the smaller the result 1 1 1

5. Step 1 — Group 1s starting with the largest cube, then next largest, etc. Step 2 — If 1 is covered by only one cube, that cube is an essential covering Step 3 — Use largest covering for 1s not covered by essential coverings Step 4 — Include singletons Step 5 — Translate to Boolean form K-map Method Summary

6. A circuit that compares two 2-bit numbers Example AB AB < CD Comparator AB = CD CD AB > CD 3 output bits 4 input bits

7. A B C D = < > 0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 1 1 1 1 0 0 0 1 1 0 1 1 Truth Table AB is one two-bit number and CD is the other AB is held constant and compared with the 4 possible values of CD Notice the three outcomes ( = < > ) are mutually exclusive 1 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 0 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 1 0 0

8. Fill in the K-maps AB CD 00 01 11 10 1 0 0 0 00 0 1 0 0 01 0 0 1 0 11 0 0 0 1 10 = AB AB CD CD 00 01 11 10 00 01 11 10 0 0 0 0 0 1 1 1 00 00 1 0 0 0 0 0 1 1 01 01 1 1 0 1 0 0 0 0 11 11 1 1 0 0 0 0 1 0 10 10 < >

9. The “=“ Function:SOP AB CD 00 01 11 10 1 0 0 0 00 0 1 0 0 01 0 0 1 0 11 0 0 0 1 10 = No simpler SOP form! Makes sense: XOR-gates! “=“ = A’B’C’D’ + A’BC’D + ABCD + AB’CD’

10. The “=“ Function: POS AB “=“ = (A C' + A' C + B D' + B' D)' = (A' + C)(A + C')(B' + D)(B + D') CD =

11. The “<“ Function: SOP AB CD 00 01 11 10 0 0 0 0 00 1 0 0 0 01 1 1 0 1 11 1 1 0 0 10 < “<“ = A’C + B’ C D + A' B‘D

12. The “<“ Function: POS AB CD < “<“ = (A C' + B C' + C' D' + A B +A D')' = (A' + C)(B' + C)(C + D)(A' + B')(A' + D)

13. The “>” Function: SOP AB CD > “>“ = AC’ + ABD’ + BC' D'

14. The “>” Function: POS AB CD > “>” = (A' C + A' D + C D + A' B' +B' C)' = (A + C')(A + D')(C' + D')(A + B)(B + C')

15. Use Logic Minimization software. Example: espresso Public domain software Easy to use, but not a toy! Used for real designs. Often the cost of a circuit depends on the number of The number of terms Number of literals. espresso tries to achieve fewer different terms. Simplifying Larger Functions

16. 3 easy Steps: Translate the given function into the espresso file format. Run espresso The espresso output file has the simplified function! a2 a1 a0 b2 b1 b0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 x x x 1 1 0 x x x 1 1 1 x x x espresso Example Minimize the following 3-input, 3-output function:

17. .i 3 .o 3 .p 8 000 001 001 010 010 011 011 100 100 000 101 --- 110 --- 111 --- .e a2 a1 a0 b2 b1 b0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 x x x 1 1 0 x x x 1 1 1 x x x Input to espresso - # input variables - # output variables - # table rows (optional) - inputs, outputs, ... - dash denotes don’t care - marks the end (optional)

18. .i 3 .o 3 .p 4 0-0 001 -11 100 -01 010 -10 010 .e This looks familiar but is new. Output Boolean expressions For each column, look for the rows that are 1, the AND terms Then OR the AND terms e.g., AND term 0-0 is a2a0 espresso Output These dashes denote absent variables b2 = a1 a0 b1 = a1' a0 + a1 a0' b0 = a2' a0'

19. minterm expression • espresso expression b2 = a2' a1 a0 b1 = a2' a1' a0 + a2' a1 a0' b0 = a2' a1' a0' + a2' a1 a0' b2 = a1 a0 b1 = a1' a0 + a1 a0' b0 = a2' a0' Comparison • 4 different terms, used 5 times. 12 literals. • 2 2-input ORs; • 4 3-input ANDs • 4 different terms, used 4 times. 8 literals. • 1 2-input OR and 4 2-input ANDs • Simpler We’ll learn to use espresso during the next studio!

20. Reference: Section 2.3 of Katz’s Textbook More K-maps Translating to/from espresso format Do Activity #1 Now

21. Boolean networks can have space-time tradeoffs. Smaller  slower. Bigger  faster. If you factor out common expressions, you may get a form with fewer gates, but with more than 2 levels of gates multilevel Multilevel Logic

22. Reduced sum of products form: X = A D F + A E F + B D F + B E F + C D F + C E F + G 6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!) 25 wires (19 literals plus 6 internal wires) A 1 D F A 2 E F A B B 1 3 D C F D B x x 2 3 4 E 4 E 7 F F C Factored form: X = (A + B + C) (D + E) F + G 1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate 10 wires (7 literals plus 3 internal wires) G 5 D F C E 6 F G Multilevel Circuits

23. SOP expressions have ANDs and ORs. You can convert it to use all NANDs (or all NORs). Necessary facts: DeMorgan's theorem Many logic chips have outputs that are active low Active low outputs are indicated by the presence of a bubble NAND-NAND networks

24. Conversion of Forms NORNAND DeMorgan's Law: (A + B)' = A' • B'; (A • B)' = A' + B' NOR is the same as AND with complemented inputs NAND is the same as OR with complemented inputs OR AND Written differently: A + B = (A' • B')'; (A • B) = (A' + B')' OR is the same as NAND with complemented inputs AND is the same as NOR with complemented inputs

25. º A A OR OR OR B B º A A NAND Nand Nand B B º A A AND AND AND B B º A A NOR NOR NOR B B Equivalent Forms

26. It is possible to convert from networks with ANDs and ORs to networks with NANDs and NORs by introducing the appropriate inversions (bubbles) To preserve logic levels, bubbles must be introduced in pairs Conversion Between Forms

27. A A (1) (2) AND B B OR C C AND D D NAND NAND (3) A A (4) B B C C D D NAND NAND NAND NAND AND/OR to NAND/NAND

28. Usedbubble-pushingto simultaneously add or remove 2 bubbles to an output and associated input. Can also just use Boolean algebra: Can also convert to NOR/NOR form. AND/OR to NAND/NAND revisited f = A B + C D (AND-OR) = ( (A B)' (C D)' )' (NAND-NAND)

29. Time Response Terms Terms: gate delay — time for change at input to cause a change at output - minimum delay vs. typical/nominal delay vs. maximum delay. - careful designers design for the worst case! propagation delay — same as gate delay rise time — time for output to transition from low to high voltage fall time — time for output to transition from high to low voltage

30. emphasis on timing behavior of circuits waveforms used to visualize what is happening use simulation to create these waveforms momentary changes of signals at the outputs: hazards can be useful — pulse shaping circuits can be a problem — glitches: incorrect circuit operation Time Response in Combinational Networks

31. 3 gate delays What happens when A changes from 0 to 1 and back again? D remains high for three gate delays after A changes from low to high F is not always 0! Time Response Example Pulse Shaping Circuit What is the value of F if A = 1? What is the value of F if A = 0?

32. Due: End of Class Today RETAIN THE LAST PAGE (#3)!! For Next Class: Bring Randy Katz Textbook Required Reading: Sec 4.1 of Katz This reading is necessary for getting points in the Studio Activity! Do Activity #2 Now