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Mobile Platform. 발표순서. Why Platform-based Design? S/W configurable platform 의 필요성 Mobile Platform. 플랫폼 (Platform). 인터넷 사회에서는 무엇인가 할만한 틀 (frame, 즉 Platform) 만 제공해주면 사람들이 몰려들어 그 도구를 이용해 새로운 가치를 제공하는 멋진 것을 만들어 냄 . Linux, wikipedia, eBay, Amazon, 싸이월드 , ….
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발표순서 • Why Platform-based Design? • S/W configurable platform의 필요성 • Mobile Platform
플랫폼(Platform) 인터넷 사회에서는 무엇인가 할만한 틀(frame, 즉 Platform)만 제공해주면 사람들이 몰려들어 그 도구를 이용해 새로운 가치를 제공하는 멋진 것을 만들어 냄. Linux, wikipedia, eBay, Amazon, 싸이월드,… In computing, a platform describes some sort of framework, either in hardware or software, which allows software to run – in Wikipedia Platform : '평평한 장소'라는 프랑스어에서 생겨난 단어
An architecture that is designed for an application domain Definition of Platforms?
Motivation • 개인의 다양한 욕구 • 상품의 life-cycle의 감소 • 무선통신 서비스의 중요성 증대 • 단말기의 소형화, 경량화, 저가격화, 고성능화 • 온-칩 통합화 (system on chip)를 통한 개발기간의 단축 및 경쟁력 제고 를 위한 설계 방법론과 검증 방법의 등장
Mobile System Complexity 4G 3.9G/ OFDM • Wide-Band Network • Ubiquitous data • Flexible Spectrum use • Enhanced apps. • 100Mbps-1Gbps • OFDM 3G 2.5G/ 2.75G • Wide-Band • Digital Cellular • Video • High-end gaming • 100Mbps, 10msec• Flexible bandwidth • All IP Network • Super 3G/LTE • OFDM (MIMO) • Wibro/WiMAX • Wide-Band • Digital • Cellular • Video • M-pixel cam. • 3D • 300kbps ~14Mbps • UMTS, HSDPA • CDMA 1X EVDO 2G • Digital • Cellular • Voice • Email • Photos • Web • ~100kbps data • GPRS/ EDGE • CDMA 2000 1X 1G • Digital • Cellular • Voice • Pager • 10kbps data • GSM, TDMA • CDMAOne • Analog • Cellular • Voice • AMPS,TACS
Challenges of Mobile SoCs • Low power and high performance • Omni-directional efforts • Whenever possible, power is off/reduced as long as the performance requirements are met • Short time-to-market • Extensive re-use of design components • Platform-based design is one of solutions
SoC and Customizable Platform Based-Design DSP Reconfigurable Hardware (Fine Grain) ASIC 2 Reconfigurable Hardware (Coarse Grain) ASIC 1
IP Blocks RTL Blocks SW Models DMA DSP CPU MPEG BUS C MEM I O Platform-Based Design • Platform • Hides unnecessary details • Targets a range of applications • Composed of basic building blocks including processors and communication fabrics Platform-based design Platform abstract Productivity increase DSP DMA cluster CPU MPEG MEM IP-based design Processor IPs Bus and other IPs
Platform 분류 • Application Platform: • 멀티미디어 platform: Nexperia, TI의 OMAP • 3G 무선 platform: Infineon의 M-gold • Bluetooth platform: Parthus • 무선 platform: ARM의 PrimeXsys • Process-centric platform • Improv System, ARC, Tensilica, Triscend • Communication-centric platform: • Sonics, Palmchip
최근 연구동향 • Intel’s Reconfigurable Radio Architecture. (mesh + nearest neighbor) • Reconfigurable Baseband Processing, Picochip • Portable Components using Containers for Heterogeneous Platforms, Mercury Computer Systems, Inc. • A configurable Platform, Altera, Excalibur, Xilinx Virtex FPGA • Adaptive Computing Machine, Quicksilver Tech. • Mercury, Sky, Galileo, Tundra (crossbars, bridges) • Virginia Tech’s reconfigurable hardware
66% chips are not OK on first silicon (2004) Mid-90s – 6 months late = > 31% earnings loss Today 3 month late = $500M loss
Full Application Platform • users design full applications on top of hardware and software architectures • Nexperia • Texas Instrument's OMAP multimedia platform • Infineon's M-Gold 3G wireless platform, • Parthus' Bluetooth platforms • ARM's PrimeXsys wireless platform
processor-centric platform • focus on access to a configurable processor but doesn't model complete applications • Improv Systems • ARC • Tensilica • Triscend
communication- centric platform • interconnect architecture but doesn't typically provide a processor or a full application • Sonics' SiliconBackplane • PalmChip's CoreFrame architectures.
fully programmable platform • consisting of FPGA logic and a processor core • Altera's Excalibur, Xilinx' Virtex-II Pro and Quicklogic's QuickMIPS • Xilinx-IBM XBlue architecture
HW-SW Kernel + Reference Design Pre-Qualified/Verified Foundation-IP* Scaleable bus, test, power, IO, clock, timing architectures MEM Hardware IP Processor(s), RTOS(es) and SW architecture CPU FPGA SW IP Programmable Foundry-Specific HW Qualification The Platform-Based Design Concept Cadence Application Space Reconfigurable Hardware Region (FPGA, LPGA, …) *IP can be hardware (digital or analogue) or software. IP can be hard, soft or ‘firm’ (HW), source or object (SW) SW architecture characterisation
Do I need a dedicated DSP ? Which micro- controller? ARM? HC11? ARC? How fast will my user interface software run? How much can I fit onto my microcontroller? Which RTOS do I use? Which scheduling policy do I have to choose ? Which Bus? PI? AMBA? Dedicated Bus for DSP? Can I buy a QCELP decoding core? Do I need a dedicated HW or can I run this on the Microcontroller ? Platform Architecture
Example of a commercial SoC More CPUs? More SRAM/Flash? Add FPGA?
Communication Broadcasting Computing Today’s Wave: Mobile - Digital Convergence • Smart Mobile Phone – A Variety of Functions • Mobile Devices • Center of Ubiquitous Media Network • Driver for Semiconductor Industry Entertainment Telematics Image Processing
미래의 모바일 컴퓨팅 • 실시간 처리 이동 슈퍼 컴퓨팅 • Speech recognition, Cryptography. • Augmented reality. • 16개의 Pentium-4 필요 • 2004 Intel P4 @3GHz; 55M TR’s 122mm2 0.09u • 2014 20GHz 0.03u • 저전력을 만족하면서 고성능 • requires (massive) parallelism • Multi-processor systems • Subsystem integration Mudge et al:
플랫폼 계층 및 구분 • Level 0: Foundation Platform • Infrastructure & standards : Basic Arch. • Processor core, Peripheral/Interface IP, Bus: e.g., ARM PrimeXsys • Level 1: Application specific Integration Platform • Application Specific SoC: HW & SW • Mobile Platform, Home Platform • Level 2: System Platform • Terminal Platform • Handset case: RF + Modem + AP + Memory + MMI
차세대 휴대 단말플랫폼 • 기존 3G 셀룰러 및 Wibro에서 Mobile TV 기능을 흡수지원: DMB 별도 시장과 경합 • PC와의 컨버젼스 경향 • 안테나: MIMO 지원을 위한 안테나 수 증가 + cellular, DMB 안테나 별도 존재 (need Convergence) • 배터리: Killer application일수록 전력 소모 증가 (need low power consumption) • Form factor: 칩 개수 증가 : 칩 셋 통합 (RF, Memory, Baseband Modem, Power Management IC, ….)
Networks-on-Silicon, Phillips Albert van der Werf, Philips Research
SDR Configuration • Modulation Format • QPSK • DQPSK • p/4 DQPSK • {16,64,256,1024} QAM • OFDM • OFDM CDMA • Digital Down/Up Conversion (DDC) • Channel Center • Decimation/Interpolation rates • Compensation Filters • Matched Filter a = {0.25,0.35,...} Soft Radio Digital Signal Processing Engine • Channel Access • CDMA • TDMA • FEC • Convolutional • Reed-Solomon • Concatenated Coding • Turbo CC/PC • (De-)Interleave • DSSS • Rake, track, acquire • Multi User Detect. (MUD) • ICU • Network Interface Definition • Security • Beam Forming
다중 Radio 통합 • 다양한 응용 서비스에 따라 다중 모드/다중 밴드 Radio 기술의 • 통합이 요구됨
개방형 인터페이스 : MIPI 노키아, TI, STMicro, ARM 등이 주도하는 MIPI (Mobile Industry Processor Interface) 표준이 더 빠르고 다양한 범위의 인터페이스 표준 채용을 촉진
OS OS Protocol stack, device driver, library, API Protocol stack, device driver, library, API Mobile Platform Voice Modem Data Modem GPS Modem core RF I/F Modem core RF I/F Security CPU (ARM) CPU (ARM) Bus Interface IPs Interface IPs Interface IPs DSP (Teak, TeakLite, StarCore) Interface IPs Bus • GSM/GPRS/EDGE/WCDMA/HSDPA/HSUPA • CDMA/CDMA2000 1x/EV-DO/EV-DV • SDMB/TDMB/DVB-H • WIBRO
FPGA Platform for Voice Modem 제어 보드 (CPU, Peripheral) Modem 보드 (Rx/Tx) SCom5700ES FPGA Board
Phase #3 – Unified Platform MCU DSP DSP RP RP RP Phase #1 – Multi Device Macro#m WCDMA Modem SOC Macro#z MCU DSP WCDMA Modem HW Core Macro#1 Macro#2 Phase #2 – Device Integration Macro#3 Macro#4 WCDMA/CDMA2000Modem SOC Macro#n Macro#m MCU DSP CDMA2000 Modem SOC WCDMA Modem HW Core Macro#1 Macro#2 Macro#3 MCU DSP CDMA2000 Modem HW Core Macro#4 CDMA2000 Modem HW Core Macro#4 Macro#5 Macro#5 Macro#6 Macro#7 Macro#6 Macro#7 Macro#k Macro#n Macro#m Macro#k Macro#m 공통된 통합 Modem Platform
Software-Defined Radio (SDR) Platform • L0 control • PHY algorithm serial portion • Symbol rate processing • Vocoder/Stereo dec. • 11GIPS 550mW • RTOS/Protocol stack 수행 • Middleware • JAVA acceleration • L1 / L2 Cache, MMU • ARM11 440MHz 220mW • High-Throughput • Low Latency: Real Time 처리 CPU DSP DSP Peripheral BUS-A Peripheral BUS Peripheral BUS-B Bridge System BUS (Display, Camera, etc.) Backbone BUS – Multi-Layer RP RP RP RP Memory Controller DDR / DDR-2 System Memory IF (FLASH / ROM / SRAM) • High Data Transfer Rate • Efficient Scheduling • Low Latency • AXI/AHB Bus ~2.5GB/sec • Application specific • Efficient processor engine • Filter/Correlator/ACS/FFT … • 51GOPS 350mW ACS: Add-Compare-Select Unit AHB: Advanced High speed Bus AXI: Advanced eXtensible Interface
SDR Platform Products Target System M/M WiBro GSM/GPRS SDR Modem RPs CPU IPs DSPs
Virtual Platform • A function-accurate and cycle-approximate hardware model in SystemC or C++ whose abstraction level is much higher than register transfer level (RTL) • 500x ~ 1000x faster simulation speed than RTL • 정량적 data를 활용한 system analysis 가능 • Code size is usually 1/5~1/3 of its corresponding RTL model • Less mistake/error, higher productivity • uses a C-level simulator • Rich debugging feautures including stop/break are provided Easy to debug Fast (system) architecture exploration and optimization is possible
Verification Platform with ARM and DSP-based Multi-processor Architecture of DVB-T Baseband Receiver