Taking LabVIEW Further into the System Level Design Domain

1. Taking LabVIEW Further into the System Level Design Domain Kaushik Ravindranand the NI Berkeley System Diagram team National Instruments, Berkeley, CA Ptolemy Mini-Conference April 16, 2009

2. National Instruments: What We Do Low-Cost Modular Measurement and Control Hardware Productive Software Development Tools Highly Integrated Systems Platforms Used By Engineers and Scientists for Test, Design and Control

3. Acoustics Temperature Monitoring Audio Waste Monitoring Body & Chassis Engine RF Signal Durability Keypad LCD Electronics Emissions Process Control Sound Safety Battery Tire & Brake Motor and Valve Control The NI Approach – Integrated Platforms PXI Modular Instrumentation Laptop PC PDA Desktop PC Dynamic Signal Acquisition High-Resolution Digitizers and DMMs Machine Vision Digital I/O Distributed I/O and Embedded Control High-Speed Digitizers Counter/ Timers Multifunction Data Acquisition Instrument Control Motion Control

4. Graphical System Design CERN Large Hadron Collider “the most powerful instrument on earth” LEGO Mindstorms NXT “the smartest, coolest toy of the year”

5. Outline • Introduction to National Instruments • System Diagram: background and motivation • Y-chart based disciplined system design methodology • Formal models • Analysis and optimization • Simulation • Verification • Summary and directions ahead

6. Virtual Instrumentation

7. Distributed Virtual Instrumentation Challenge: How to efficiently and productively deploy high performance applications on these multi-target platforms?

8. Challenge: The Implementation Gap Concurrent Application • Application trends • 1000’s of parallel tasks • Large node/channel counts • High performance requirements • E.g. streaming DSP applications CLIP How to map the tasks and data in a concurrent application to the processing and memory resources in a multi-target platform? Implementation Gap Multi-Target Platform • Platform trends • 100’s of processing elements • Heterogeneous processors and memories • Distributed I/O • E.g. FPGA targets

9. System Diagram A single canvas to clearly model hardware and software to increase user productivity and application performance Goal: Make graphical system design of distributed high-speed multi-rate applications on heterogeneous multi-target platforms 5-10x easier than current tools

10. The System Diagram Charter • Deliver a framework with rich visualization of application and platform and support it with an exploration methodology • Hierarchical composition of mixed models of computation • Single canvas to model hardware and software • Support systems with large node and channel counts • Rapid design space exploration • Tune for high-speed multi-rate streaming applications with asynchronous IP deployed on heterogeneous multi-target platforms

11. Outline • Introduction to National Instruments • System Diagram: background and motivation • Y-chart based disciplined system design methodology • Formal models • Analysis and optimization • Simulation • Verification • Summary and directions ahead

12. Y-Chart: A Disciplined System Design Methodology Application Model (and Constraints) Platform Model (and Constraints) Representative formal models Analysis and Mapping Efficient analysis and optimization Performance Evaluation Fast and accurate simulation Reliable verification Deployment [1] B. Kienhuis, E. F. Deprettere, P. Wolf, K. A. Vissers. “A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach”. SAMOS, p.18-37, Jan 2002.

13. Analogy: EDA Design Flow for VLSI Circuits moduleFull_Adder (sum, c_out, a, b, c_in); output [3:0] sum; output c_out; input [3:0] a, b; inputc_in; assign {c_out, sum} = a + b + c_in; endmodule HDL Simulation HDL Representative formal models Library / Module Generators RTL Synthesis Behavior verification moduleFull_Adder (sum, c_out, a, b, c_in); output [3:0] sum; output c_out; input [3:0] a, b; inputc_in; wire c_in2, c_in3, c_in4; Full_adder M1(sum[0], c_in2, a[0], b[0], c_in); Full_adder M2(sum[1], c_in3, a[1], b[1], c_in2); Full_adder M3(sum[2], c_in4, a[2], b[2], c_in3); Full_adder M4(sum[3], c_out, a[3], b[3], c_in4); endmodule RTL Simulation RTL Efficient analysis and optimization Logic Optimization Equivalence verification Gate Level Simulation Netlist Fast and accurate simulation Circuit/design rule verification Physical Design Reliable verification Circuit Simulation Layout Courtesy: Prof. Kurt Keutzer, EE244 Lecture 1, UC Berkeley

14. Bringing EDA to System Diagram • Objective: Advance a disciplined (possibly automated) design methodology to help designers evaluate large design spaces and create successful system deployments • Imperatives for disciplined design • Well-defined abstractions, system-level semantics • Systematic flow from specification to deployment • Imperatives for automation support • Accurate models and constraints • Efficient analysis, simulation, and verification methods

15. Outline • Introduction to National Instruments • System Diagram: background and motivation • Y-chart based disciplined system design methodology • Formal models • Analysis and optimization • Simulation • Verification • Summary and directions ahead

16. System Diagram Application Model • Application processes streams of data • Application is composed of tasks • Tasks differ in rate of data produced and consumed • Tasks differ in rate of executions in time • Application has real-time throughput and latency requirements on its I/O Goals: (1) Identify formal multi-rate models relevant to System Diagram (2) Propose intuitive multi-rate representations (3) Support integration with 3rd-party libraries and IP

17. MoCs for Streaming Applications Deter- ministic? No Yes No Yes Synchronous? NoYes No Yes Deadlock and boundedness decidable? Static scheduling? Heterochronous Dataflow Kahn Process Networks SHIM Static Dataflow Expressive Analyzable Boolean Dataflow Cyclo-static Dataflow Homogeneous Dataflow Process Networks Integer Dataflow Key trade-off: Analyzability vs. Expressibility [1] Edward A. Lee, “Concurrent Models of Computation for Heterogeneous Software”, EECS 290, 2004. [2] Stephen Edwards, “SHIM: A Deterministic Model for Heterogeneous Embedded Systems”, UCB EECS Seminar, 2006. [3] Thanks: Abhijit Davare, UCB.

18. Language Design Challenge • How to constrain application models in SD so that they are amenable to efficient analysis, simulation, and synthesis? • How to balance expressiveness and analyzability of models in an unified framework? • How to enable heterogeneity in composition of models? • How to verify model transformations and refinements?

19. Outline • Introduction to National Instruments • System Diagram: background and motivation • Y-chart based disciplined system design methodology • Formal models • Analysis and optimization • Simulation • Verification • Summary and directions ahead

20. Static Models, Static Methods c a b The Mapping Step in the Y-Chart Methodology • Assume knowledge of workload and parallel tasks at compile time • Viable for rapid design space exploration • Useful for fast exploration of “what-if” scenarios • Desired properties of static methods • Computationally efficient • Easy problem capture • Flexible and extensible • Near-optimal solutions Architecture model Application model and profiles P1 P2 P3 P4 Static Task Allocation and Scheduling Implementation and Performance Analysis

21. Static Task Allocation and Scheduling P1 P2 Platform Model Task Dependence Graph (with execution times) • Scheduling problem • Fix each task to a processor • Find start time for each task • Enforce dependencies • Minimize makespan 3 b 3 7 a d 3 c 5 2 3 g e f 6 h static-level (v) = delay of longest path from v to a sink vertex List Scheduling Heuristic Time Makespan = 18 (sub-optimal) [1] Gilbert. C. Sih and Edward. A. Lee, "A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures," IEEE Transactions on Parallel and Distributed Systems, 4(2):175-187, 1993.

22. Worst Case Execution Time Analysis • Problem: Given a G program, fixed target (host, RT, FPGA), and timing estimates of primitive blocks, compute average or worst case execution time of the program on the target Example: Compute worst case number of cycles for FPGA VIs (assume bounded iterations, no recursive behavior)

23. Related Compile Time Analysis Problems • Verify determinism • Verify liveness • Verify boundedness • Verify consistency of multi-rate applications • Verify type consistency • Verify interface match • Select hardware components given budget • Verify configuration and wiring Application / Workload Multi-target Platform • Optimize buffer sizes given throughput • Compute worst case task execution times • Compute cycle delay for FPGA-bound tasks • Compute load balance given throughput • Minimize total communication costs • Schedule communications for fixed task allocation • Compute data layout for fixed task allocation Analysis and mapping • Estimate throughput given schedule • Verify application and platform constraints • Verify timing constraints • Verify equivalence of design refinements Performance Evaluation

24. Outline • Introduction to National Instruments • System Diagram: background and motivation • Y-chart based disciplined system design methodology • Formal models • Analysis and optimization • Simulation • Verification • Summary and directions ahead

25. Analysis Methods for System Diagram Accuracy Performance Analysis Methods Efficiency low high Static analysis Analysis without program execution (compile time) Simulation Analysis based on dynamic execution of restricted application and platform models Synthesis Analysis following full system deployment high low

26. Simulation Techniques Communication VIs w/ cycle accurate timing + CT timing Exact- timed Hybrid Implementation model Target dependent, system-plant co-simulation VIs w/ cycle accurate timing Cycle- timed Implementation model Target dependent,cycle accurate simulation VIs w/ approximated timing Approximate- timed Bus-arbitration model Target dependent, timed behavioral simulation Untimed VIs Spec model Untimed Target independent,behavioral simulation Computation Untimed Approximate- timed Cycle- timed Exact- timed Less accurate models, faster simulations More accurate models, slower simulations

27. Outline • Introduction to National Instruments • System Diagram: background and motivation • Y-chart based disciplined system design methodology • Formal models • Analysis and optimization • Simulation • Verification • Summary and directions ahead

28. Verification Challenges in the Design Flow Is the application deterministic and deadlock-free? Application / Workload Multi-target Platform CLIP Analysis and Mapping Are model refinements equivalent? Application Model Platform Model Does the mapping satisfy application and platform constraints? Mapping model Platform Constraints Application Constraints Allocation/Scheduling Does the implementation meet real-time performance constraints? Performance Evaluation Is the implementation accurate for user-defined and auto-generated testbenches?

29. Outline • Introduction to National Instruments • System Diagram: background and motivation • Y-chart based disciplined system design methodology • Formal models • Analysis and optimization • Simulation • Verification • Summary and directions ahead

30. Y-Chart: A Disciplined System Design Methodology Application Model (and Constraints) Platform Model (and Constraints) Representative formal models Analysis and Mapping Efficient analysis and optimization Performance Evaluation Fast and accurate simulation Reliable verification Implementation [1] B. Kienhuis, E. F. Deprettere, P. Wolf, K. A. Vissers. “A Methodology to Design Programmable Embedded Systems - The Y-Chart Approach”. SAMOS, p.18-37, Jan 2002.

31. Directions Ahead • Improved application and platform models • More expressive models of computation • Accurate static performance models • Other compile time optimization problems • Communication scheduling and data layout • Deadlock, unboundedness detection • Simulation and verification support • Untimed/timed system level simulation, FPGA co-simulation • Testbench generation, IP interface verification • Applications and use cases • RF, radios, mobile communications, real-time control

32. NI Berkeley - Cast and Crew • Hugo Andrade • SadiaMalik • Mike Rauser • KaushikRavindran • Trung Tran • Gerald Wang • Guang Yang