HDL/PLI Test Toolbox

1. HDL/PLI Test Toolbox East-West 2009 Nastaran Nemati Majid Namaki Shoushtari Prof. Zainalabedin Navabi University of Tehran

2. Contents • Motivations • PLI Test Package • Features of the Test Package • Fault Injection • Fault Collapsing • Fault Simulation • DFT Evaluation • Other Applications • Experimental results • Summary and Conclusions

3. Motivations :Why HDL Test? • Design methods are going to higher levels of abstraction • Digital system test stays at the gate level • It must get advanced to RT level

4. Motivations :Why HDL Test? • Gap between Design and Test Engineers • Results: • More test time • More test effort • Less testable designs

5. Motivations : Why HDL Test? • The most important RT level tools are those that are based on VHDL and Verilog • Developing test methods compatible with such hardware description languages • Benefits: Having both design and its testbench in an uniform environment

6. Motivations : HDL Limitations • The overhead of test methods on simulation speed • Inaccessibility of HDL internal data structure • Solution: PLI

7. What is PLI? • Procedural Language Interface • A library of C language functions • Accessible to the compiled Verilog data structure • Enables the test engineer to explore the design modules, ports, nets, etc., easily

8. PLI Test Package Flow PLI Function Test Program

9. Features of Test Package • Fault Injection • Fault Collapsing • Fault Simulation • DFT Evaluation • Other Applications • DFT reconfiguration

10. Fault Injection • Stuck@Fault • Transient fault • Bridging fault • Coupling fault

11. Stuck@ Fault accForceValue accReleaseValue

12. Stuck at Fault Injection and Removal • Just write the value of fault wherever desired • Simply using access functions • $InjectFault(wireName, stuck@val); • $RemoveFault(wireName);

13. Transient Fault Injection • Delay setting is possible • Transient fault injection • $TransientFault(wireName, FaultValue, faultDuration)

14. Bridging Fault Injection $BridgingFault(line1, line2, “and”); $BridgingFault(line1, line2, “or”); $RemoveBridgingFault(line1, line2); acc_vcl_add (variable_object, consumer_routine) acc_vcl_delete (variable_object)

15. Coupling Fault Injection $CouplingFault(FF1, FF2); $RemoveCouplingFault(FF1, FF2);

16. Fault Collapsing

17. Serial Fault Simulation $faultCollapsing $InjectFault(wireName, faultValue) $RemoveFault(wireName)

18. Parametric DFT and DFT Evaluation • Parametric DFTs • Scan evaluation • BIST evaluation

19. Summary • A convenient and easy to use environment for test applications in Verilog HDL using PLI is presented. • Develop test applications while having the flexibility of any desired combination of available methods. • Evaluate DFT in an virtual tester and use this evaluation to design optimized test programs. • Access routines of PLI makes the development of test methods, easier and with no mingling in the original design core. • The results of PLI fault simulator are close enough to those the stand-alone test application programs. • Providing test methods in PLI, test designers can benefit from both HDL test and high speed software test. • Using the applications and utilities of this test toolbox is very simple and effortless.

20. References • C. J. Hesscot, D. C. Ness, and D. J. Lilja, “A Methodology for Stochastic Fault Simulation in VLSI Processor Architectures,” In MoBs, 2005. • IEEE Std 1364 – 2001, clause 20 through clause 25 • M. Nadjarbashi, Z. Navabi and M. R. Movahedin, “Line Oriented Structural Equivalence Fault Collapsing,” in IEEE Workshop on Model and Test, 2000. • N. Farajipour, S. B. Hosseini and Z. Navabi, “Utilizing HDL Simulation Engines for Accelerating Design and Test Processes,” In IEEE Int. East-West Design and Test Symposium , 2008. • P. A. Riahi, Z. Navabi, and F. Lombardi, “Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment,” DFT, 2005. • Z. Navabi, “VHDL: Modular Design and Synthesis of Cores and Systems,” McGraw Hill, 1998. • Z. Navabi, S. Mirkhani, M. Lavasani, and F. Lombardi, “Using RT-Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation,” Journal of Testing: Theory and Applications (JETTA), Vol. 20, No. 6, December 2004. • M. L. Bushnell and V. D. Agrawal, "Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits", Kluwer Academic Publishers, 2000, pp. 256-257.

21. Thanks For Listening Questions?