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Introduction To Computer Architecture

Introduction To Computer Architecture. Jean-Michel RICHER University of Angers France richer@info.univ-angers.fr January 2003. WARNING !. This document can be reproduced, modified and used freely. Please report any change or improvement to Jean-Michel Richer at :

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Introduction To Computer Architecture

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  1. Introduction To Computer Architecture Jean-Michel RICHER University of Angers France richer@info.univ-angers.fr January 2003

  2. WARNING ! This document can be reproduced, modified and used freely. Please report any change or improvement to Jean-Michel Richer at : richer@info.univ-angers.fr (http://www.info.univ-angers.fr/pub/richer) January 2003

  3. OUTLINE • Memory organization • Some CPU organizations • Example of program execution with the Intel 8086 • Example of program execution with pipeline technology

  4. Code contains the program code Data contains the program data contains subprograms calls HEAP contains the rest of the memory STACK MEMORY ORGANIZATION The operating system organizes the memory as follows :

  5. DIFFERENT CPU ORGANIZATIONS 8086 80486 Pentium III Pentium IV

  6. Code Data HEAP STACK Intel 8086 Instruction path Cpu die motherboard Load Instruction Registers Decode Data path Load Operand Execute ALU Coprocessor Write Result

  7. L1 Cache L1 Cache - I Code L2 Cache Data FPU L2 Cache on Motherboard HEAP STACK Integrated FPU Intel 80486 Load Instruction Registers Decode Load Operand Execute ALU Write Result

  8. Branch Prediction Code BTB TLB L1 Cache - D Data ALU 1 ALU 2 L1 Cache HEAP Superscalar STACK Intel Pentium L1 Cache - I Load Instruction L2 Cache Registers Decode Load Operand Execute FPU Write Result

  9. Code Data L2 Cache on-die HEAP STACK Intel Pentium III L1 Cache - I BTB TLB Load Instruction L2 Cache L1 Cache - D Registers Decode Load Operand Execute ALU 1 ALU 2 FPU Write Result

  10. Trace Cache Code Trace Cache Data HEAP STACK Intel Pentium IV BTB TLB Load Instruction L2 Cache L1 Cache - D Registers Decode Load Operand Execute UAL 1 UAL 2 FPU Write Result

  11. PROGRAM EXECUTION The 8086 case

  12. Assembler 8086 mov ax, [100] mov bx, [102] add ax, bx mov [104], ax (a) 100 0000000000000001 (b) 102 0000000000000010 (c) 104 0000000000000000 Program C Language int a, b ,c a = 1; b = 2; c = a + b

  13. OP Value 1 Value 2 R1 R2 2 bits 16 bits 16 bits 2 bits 2 bits 00 mov r1,[adr] 01 mov [adr],r1 11 add r1,r2 00 AX 01 BX 10 CX 11 DX Micro code Instructions are converted into micro-operations that can be handled by the CPU (Central Processing Unit) of the micro-processor Operation Values Registers

  14. Load Instruction Decode Load Operand Execute UAL Write Result STACK Starting point mov ax,[100] mov bx,[102] add ax, bx mov [104],ax Registers AX=? [100]=1 [102]=2 [104]=0 BX=? CX=? DX=? HEAP

  15. STACK Load Instruction : mov ax,[100] mov ax,[100] mov bx,[102] add ax, bx mov [104],ax mov ax,[100] Registers Decode AX=? Load Operand [100]=1 [102]=2 [104]=0 BX=? CX=? Execute DX=? UAL Write Result HEAP

  16. STACK Decode Instruction : mov ax,[100] Micro code op val1 val2 r1 r2 00 100 ? 00 ? mov ax,[100] mov bx,[102] add ax, bx mov [104],ax mov ax,[100] Registers 00 100 ? 00 ? AX=? Load Operand [100]=1 [102]=2 [104]=0 BX=? CX=? Execute DX=? UAL Write Result HEAP

  17. STACK Load operand : mov ax,[100] Micro code op val1 val2 r1 r2 00 100 1 00 ? mov ax,[100] mov bx,[102] add ax, bx mov [104],ax mov ax,[100] Registers 00 100 ? 00 ? AX=? 00 100 1 00 ? [100]=1 [102]=2 [104]=0 BX=? CX=? Execute DX=? UAL Write Result HEAP

  18. STACK Execute : mov ax,[100] mov ax,[100] mov bx,[102] add ax, bx mov [104],ax mov ax,[100] Registers 00 100 ? 00 ? AX=? 00 100 1 00 ? [100]=1 [102]=2 [104]=0 BX=? CX=? Execute DX=? UAL Write Result HEAP

  19. STACK Write result : mov ax,[100] mov ax,[100] mov bx,[102] add ax, bx mov [104],ax mov ax,[100] Registers 00 100 ? 00 ? AX=1 00 100 1 00 ? [100]=1 [102]=2 [104]=0 BX=? CX=? Execute DX=? UAL 00 100 1 00 ? HEAP

  20. STACK Load Instruction : mov bx,[102] mov ax,[100] mov bx,[102] add ax, bx mov [104],ax mov bx,[102] Registers Decode AX=1 Load Operand [100]=1 [102]=2 [104]=0 BX=? CX=? Execute DX=? UAL Write Result HEAP

  21. STACK Decode Instruction : mov bx,[102] Micro code op val1 val2 r1 r2 00 102 ? 01 ? mov ax,[100] mov bx,[102] add ax, bx mov [104],ax mov bx,[102] Registers 00 102 ? 01 ? AX=1 Load Operand [100]=1 [102]=2 [104]=0 BX=? CX=? Execute DX=? UAL Write Result HEAP

  22. STACK Load operand : mov bx,[102] Micro code op val1 val2 r1 r2 00 102 2 01 ? mov ax,[100] mov bx,[102] add ax, bx mov [104],ax mov bx,[102] Registers 00 102 ? 01 ? AX=1 00 102 2 00 ? [100]=1 [102]=2 [104]=0 BX=? CX=? Execute DX=? UAL Write Result HEAP

  23. STACK Execute : mov bx,[102] mov ax,[100] mov bx,[102] add ax, bx mov [104],ax mov bx,[102] Registers 00 102 ? 01 ? AX=1 00 102 2 00 ? [100]=1 [102]=2 [104]=0 BX=? CX=? Execute DX=? UAL Write Result HEAP

  24. STACK Write result : mov bx,[102] mov ax,[100] mov bx,[102] add ax, bx mov [104],ax mov bx,[102] Registers 00 102 ? 01 ? AX=1 00 102 2 01 ? [100]=1 [102]=2 [104]=0 BX=2 CX=? Execute DX=? UAL 00 102 2 01 ? HEAP

  25. STACK Load Instruction : add ax,bx mov ax,[100] mov bx,[102] add ax, bx mov [104],ax add ax,bx Registers Decode AX=1 Load Operand [100]=1 [102]=2 [104]=0 BX=2 CX=? Execute DX=? UAL Write Result HEAP

  26. STACK Decode Instruction : add ax,bx Micro code op val1 val2 r1 r2 11 ? ? 00 01 mov ax,[100] mov bx,[102] add ax, bx mov [104],ax add ax,bx Registers 11 ? ? 00 01 AX=1 Load Operand [100]=1 [102]=2 [104]=0 BX=2 CX=? Execute DX=? UAL Write Result HEAP

  27. STACK Load Operand : add ax,bx Micro code op val1 val2 r1 r2 11 1 2 00 01 mov ax,[100] mov bx,[102] add ax, bx mov [104],ax add ax,bx Registers 11 ? ? 00 01 AX=1 11 12 00 01 [100]=1 [102]=2 [104]=0 BX=2 CX=? Execute DX=? UAL Write Result HEAP

  28. STACK Execute : add ax,bx Micro code op val1 val2 r1 r2 11 3 2 00 01 mov ax,[100] mov bx,[102] add ax, bx mov [104],ax add ax,bx Registers 11 ? ? 00 01 AX=1 11 1 2 00 01 [100]=1 [102]=2 [104]=0 BX=2 CX=? Execute DX=? 1+2 11 3 2 00 01 Write Result HEAP

  29. STACK Write Result : add ax,bx mov ax,[100] mov bx,[102] add ax, bx mov [104],ax add ax,bx Registers 11 ? ? 00 01 AX=3 11 1 2 00 01 [100]=1 [102]=2 [104]=0 BX=2 CX=? Execute DX=? 11 3 2 00 01 11 3 2 00 01 HEAP

  30. STACK Load Instruction : mov [104],ax mov ax,[100] mov bx,[102] add ax, bx mov [104],ax mov [104],ax Registers Decode AX=3 Load Operand [100]=1 [102]=2 [104]=0 BX=2 CX=? Execute DX=? UAL Write Result HEAP

  31. STACK Decode Instruction : mov [104],ax Micro code op val1 val2 r1 r2 01 104 ? 00 ? mov ax,[100] mov bx,[102] add ax, bx mov [104],ax mov [104],ax Registers 01 104 ? 00 ?? AX=3 Load Operand [100]=1 [102]=2 [104]=0 BX=2 CX=? Execute DX=? UAL Write Result HEAP

  32. STACK Load Operand : mov [104],ax Micro code op val1 val2 r1 r2 01 104 3 00 ? mov ax,[100] mov bx,[102] add ax, bx mov [104],ax mov [104],ax Registers 01 104 ? 00 ?? AX=3 01 104 3 00 ?? [100]=1 [102]=2 [104]=0 BX=2 CX=? Execute DX=? UAL Write Result HEAP

  33. STACK Load Operand : mov [104],ax Micro code op val1 val2 r1 r2 01 104 3 00 ? mov ax,[100] mov bx,[102] add ax, bx mov [104],ax mov [104],ax Registers 01 104 ? 00 01 AX=3 01 104 3 00 01 [100]=1 [102]=2 [104]=0 BX=2 CX=? Execute DX=? UAL Write Result HEAP

  34. STACK Write Result : mov [104],ax mov ax,[100] mov bx,[102] add ax, bx mov [104],ax mov [104],ax Registers 01 104 ? 00 01 AX=3 01 104 3 00 01 [100]=1 [102]=2 [104]=3 BX=2 CX=? Execute DX=? UAL 01 104 3 00 01 HEAP

  35. PROGRAM EXECUTION WITH PIPELINE Pentium-Like

  36. DEPENDENCIES The 8086 code shows there are 2 dependencies : mov ax, [100] mov bx, [102] add ax, bx mov [104], ax RAW Forward WAW Forward

  37. AVOID DEPENDENCIES To avoid dependencies we can add a field to the micro-code in order to indicate when data need to be forwarded into the pipeline : Operation Values Registers Flag OP Value 1 Value 2 R1 R2 F 2 bits 16 bits 16 bits 2 bits 2 bits 1 bit If F = 1 then Forward Data

  38. TRADUCTION INTO MICRO-OPs op val1 val2 r1 r2 f mov ax, [100] mov bx, [102] add ax, bx mov [104], ax 00 100 ? 00 ? 0 00 102 ? 01 ? 1 11 ? ? 00 01 1 01 104 ? 00 ? 0

  39. Step 1 Load Operand : mov ax,[100] 00 100 ? 00 ? 0 Load Operand 1 Execute UAL Write Result

  40. Step 2 00 102 ? 01 ? 1 00 100 1 00 ? 0 Execute : mov ax,[100] Load Operand : mov bx,[102] Load Operand 2 Execute UAL Write Result

  41. Step 3 11 ? ? 00 01 1 00 102 2 01 ? 1 AX=1 00 100 1 00 ? 0 Write Result : mov ax,[100] Execute : mov bx,[102] Load Operand : add ax,bx Forward result Load Operand 1 2 Execute 1 UAL Write Result

  42. Step 4 Write Result : mov bx,[102] Execute : add ax, bx Load Operand : mov [104],ax Forward result 01 104 3 ? 00 ? 0 11 1 2 00 01 1 1+2 11 3 2 00 01 1 1 BX=2 00 102 2 01 ? 1 Load Operand Execute UAL Write Result

  43. Step 5 Write Result : add ax, bx Execute : mov ax,[104] 01 104 3 00 ? 0 AX=3 11 3 2 00 01 1 Load Operand Execute UAL Write Result

  44. Step 6 Write Result : mov ax, [104] Load Operand Execute UAL Write Result 01 104 3 00 ? 0 RAM

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