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CSC 3650 Introduction to Computer Architecture. Spring 2011. Time: 3:30 to 6:30. Meeting Days: W. Location: Oxendine 1237B. Textbook : Essentials of Computer Architecture , Author: Douglas E. Comer, 2005, Pearson Prentice Hall. Introduction to Computer Architecture. Dr. Chuck Lillie.
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CSC 3650 Introduction to Computer Architecture Spring 2011 Time: 3:30 to 6:30 Meeting Days: W Location: Oxendine 1237B Textbook: Essentials of Computer Architecture, Author: Douglas E. Comer, 2005, Pearson Prentice Hall Introduction to Computer Architecture Dr. Chuck Lillie
Computer Architecture • Central Processing Unit • Memory • Input/Output
Instruction Cycle • Microprocessor places address of instruction on address bus • Memory subsystem inputs address and decodes it • After allowing time for address to be decoded, microprocessor issues a read control signal • Data is placed on data bus • Data is taken from data bus and placed in register • Microprocessor decodes the instruction • Instruction is executed Memory Read Memory Write
CPU Internal Organization READ, WRITE, IO/M Program counter Instruction register General purpose Instruction code Flag values Operations to perform
Types of Memory • Read Only Memory (ROM) • Masked ROM: programmed with data as chip is fabricated • Programmable Read Only Memory (PROM): can be programmed by user, but only once • Erasable PROM (EPROM): content can be erased and reprogrammed • Electrically Erasable PROM (EEPROM): can modify individual locations on the EEPROM • Chip with 2n words, each having m bits, has n address inputs, An-1 to A0, and m data outputs, Dm-1 to D0 • D is used as input to program chip • Has chip enable (CE), output enable (OE), and program control input (Vpp) • CE must be active for something to happen
Types of Memory • Random Access Memory (RAM) • Dynamic RAM (DRAM): like leaky capacitors, if not refreshed will eventually loose data. Used for primary memory. • Static RAM (SRAM): Does not have to be refreshed. Faster than DRAM but more expensive. Used for cache memory. • Each 2n X m chip has n address inputs and m bidirectional data pins • Chips have chip enable (CE or CE’) • Chips may have either read enable input (RD or RD’) and write enable (WR or WR’) or one combined signal, such as R/W’ . R/W’ would be set to 1 for read and 0 for write. • CE must be active for read or write to happen
Internal Linear Organization of 8 X 2 ROM Chip Three address inputs, two data outputs, and 16 bits of internal storage arranged as eight 2-bit locations The three addrss bits are decoded to select one of the eight locations
Internal two-dimensional organization fo an 8 X 2 ROM chip Two high order bits select one of the four rows, the low order bit selects the two desired bits Four rows with four bits per row Top row holds bits for address 000 and 001, second row address 010 and 011
16 X 2 memory subsystem constructed from two 8 X 2 ROM chips with high-order interleaving Upper chip always has A3 = 0 and the lower chip always has A3 = 1 Upper chip has addresses 0000 to 0111 Lower chip has addresses 1000 to 1111
16 X 2 memory subsystem constructed from two 8 X 2 ROM chips with low-order interleaving Upper chip enabled for A0 = 0, or addresses 0, 2, 4, 6, 8, 10, 12, 14 Lower chip enabled for A0 = 1, or addresses 1, 3, 5, 7, 9, 11, 13, 15 Low order interleaving offers speed advantages for pipelined memory access
8 X 4 memory subsystem constructed from two 8 X 2 ROM chips with control signals Output enable is just the RD signal from the CPU 6-bit address Use 3 low order bits for chip location Use 3 high order bits for chip enable (all must be 0 for chip to be active
An Input Device Enable logic for tri-state buffers I/O device address is 11110000 Interface
An Output Device Tri-state buffers are not need for output because the data is put on the data bus and only the device at the address buss address will read the data from the data bus
Bidirectional input/output device with its interface and enable/load logic
