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CMOS CLOCK-RELATED CIRCUIT DESIGN. Integrated Circuits Spring 2001 Dept. of ECE University of Seoul. Non-Overlapping 2-Phase Clocks 1. Using sequential circuits (e.g. counters) & some logics, f 1 & f 2 can be generated from f 0 . for Accurate Control of Timing Schemes
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CMOS CLOCK-RELATED CIRCUIT DESIGN Integrated Circuits Spring 2001 Dept. of ECE University of Seoul
Non-Overlapping 2-Phase Clocks 1 • Using sequential circuits (e.g. counters) & some logics, • f1 & f2 can be generated from f0. • for Accurate Control of Timing Schemes • for High-Speed Clocks
Driving Large Load Capacitance 1 • Method 1 : Single Buffer Method 2 : Cascade of Buffers Better Choice How Many Stages & Scaling?
Driving Large Load Capacitance 2 • Inverter Delay 1 Inverter Delay 2 Inverter Delay 3
Driving Large Load Capacitance 3 • Chain of Inverters
Driving Large Load Capacitance 4 • In order to Achieve Minimum Delay • For Example, Cd=0 a=e=2.718 • For Example, Cd=5fF, Cg=10fF, CL=50pF • 7 inverters to be cascaded w/ increasing size scaling of 3.18