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CEG3470 REVISION LECTURE (Some slides from Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response)

CEG3470 REVISION LECTURE (Some slides from Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response). David Harris Harvey Mudd College Spring 2004. Outline. Transistor capacitances Transistor properties (current & capacitance vs size & voltage)

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CEG3470 REVISION LECTURE (Some slides from Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response)

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  1. CEG3470 REVISION LECTURE(Some slides from Introduction toCMOS VLSI DesignLecture 4: DC & Transient Response) David Harris Harvey Mudd College Spring 2004

  2. Outline • Transistor capacitances • Transistor properties (current & capacitance vs size & voltage) • Inverter transfer function regions of operation 4: DC and Transient Response

  3. Polysilicongate Source Drain W x x + + n n d d Gate-bulk L d overlap Top view Gate oxide t ox + + n n L Cross section The Gate Capacitance 4: DC and Transient Response

  4. Diffusion Capacitance Channel-stop implant N 1 A Side wall Source W N D Bottom x Side wall j Channel L Substrate N S A 4: DC and Transient Response

  5. Activity 1)If the width of a transistor increases, the current will  increase decrease not change 2)If the length of a transistor increases, the current will increase decrease not change 3)If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4)If the width of a transistor increases, its gate capacitance will increase decrease not change 5)If the length of a transistor increases, its gate capacitance will increase decrease not change 6)If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change 4: DC and Transient Response

  6. Transistor Operation • Current depends on region of transistor behavior • For what Vin and Vout are nMOS and pMOS in • Cutoff? • Linear? • Saturation? 4: DC and Transient Response

  7. nMOS Operation 4: DC and Transient Response

  8. nMOS Operation 4: DC and Transient Response

  9. nMOS Operation Vgsn = Vin Vdsn = Vout 4: DC and Transient Response

  10. nMOS Operation Vgsn = Vin Vdsn = Vout 4: DC and Transient Response

  11. pMOS Operation 4: DC and Transient Response

  12. pMOS Operation 4: DC and Transient Response

  13. pMOS Operation Vgsp = Vin - VDD Vdsp = Vout - VDD Vtp < 0 4: DC and Transient Response

  14. pMOS Operation Vgsp = Vin - VDD Vdsp = Vout - VDD Vtp < 0 4: DC and Transient Response

  15. Operating Regions • Revisit transistor operating regions 4: DC and Transient Response

  16. Operating Regions • Revisit transistor operating regions 4: DC and Transient Response

  17. Noise Margins • How much noise can a gate input see before it does not recognize the input? 4: DC and Transient Response

  18. Midterm • All material in slides on website • Test understanding of the material • Equation summary (same as for 2007 midterm provided) • 4 Questions • Devices and manufacturing (transistor equations, capacitance model, secondary effects, simplified process flow, transistor cross section) • Wire (RLC, Elmore delay, distributed rc model) • Inverter (switching threshold, noise margins, delay, power, energy) • Buffer sizing (to minimise delay, energy, power) 4: DC and Transient Response

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