Toward Nano-Networks and Architectures C. Gerousis and D. Ball

1. Toward Nano-Networks and Architectures C. Gerousis and D. Ball Department of Physics, Computer Science and Engineering Christopher Newport University Newport News, VA 23606

2. Nanoelectronic Architectures • Limits of Conventional CMOS technology • - Device physics scaling, power dissipation • - Interconnects • Nanoelectronic Integrated Circuits - Hybrid circuits of ultrascale CMOS coupled to locally connected cellular nonlinear networks (CNNs) of nanodevices for special purpose processing • Present Work -Simulation of nano networks synthesized from single-electron tunneling transistors (SETs) -Demonstration of SET-CNN and SET neural applications 2

3. Photo-detector Single-electron transistors as processing elements CMOS drivers for fan-out Nanoelectronic Integrated Circuit CMOS and SETs are rather complementary: SET is the winner of low-power consumption and of new functionality while the advantages of CMOS such as high-speed, driving, voltage gain and input impedance can makeup for exactly for the SET's intrinsic shortcomings. 3

4. Single-Electron Transistor A single-electron tunneling (SET) transistor composed of a conducting island (or quantum dot) between two tunnel junctions characterized by junction capacitances, Cs and Cd, and tunneling resistances, Rs and Rd. 4

5. G/Gmax 1 e 0 EFr Vg(e/Cg) EFl 0 1 2 3 Single-Electron Transistor Electron tunneling is suppressed due to the Coulomb charging energy, e2/2C. A separate gate voltage changes the charge state of the dot (island), and periodically lifts the Coulomb blockade allowing tunneling. Si SOI Single Electron Transistor: D. H. Kim et al., IEEE Trans. ED49, 2002 5

6. Monte Carlo simulation of SET circuits The Master Equation for a set of N dots (islands) in terms of the multi-island distribution function is given by where the tunneling rate depends on change of total free energy of systems after tunneling 6

7. Monte Carlo simulation of SET circuits Average quantities such as current in a two junction system are given as averages Single electron tunnel events modeled as instantaneous events which are generated stochastically using the calculated tunneling rates for all possible events across all junctions, and using the computer random number generator where r is random number 0,1 and tr is the random time between tunneling events. After tunneling, the new tunnel rates are computed, and the next tunneling event generated. The time evolution according to the master equation is modeled as random walk. 7

8. ‘SIMON’ (SIMulation Of Nano structures) C. Wassshuber and H. Kosina, "SIMON: A Single-Electron Device and Circuit Simulator", Superlattices and Microstructures21, 37 (1997). 8

9. xij xij Feedback synapses Feedforward synapses SET Cellular Nonlinear Networks A non-linear architecture suitable for SET devices is a locally interconnected CNN type array structure for use in array processing such as image processing applications. The center cell, Cij, receives a weighted feedforward signal bklukl and a weighted feedback signal aklyklfrom each neighboring cell Ckl. 9

10. y 1 x -1 Cellular Nonlinear Networks Cell state equation: Cell output equation: Transfer function: 10

11. Template: C12=C23=0.55aF C11=C22= C22=0.1aF Single-Electron Cellular Network - Shadowing 11

12. Threshold Gate in SET Networks • A threshold gate can be described by the following equations: where ω are the weights, x represents the inputs, and ψ is the threshold Model of a TLG with SET technology (Lageweg et al.) 12

13. Threshold Gate - SET inverter Model of a TLG with SET technology (Lageweg et al.) 13

14. V1 V2 V3 V4 Vout Network for Recognition of Bit Pattern 1111 1001 14

15. V1 V2 V3 V4 Vout Network for Recognition of Bit Pattern 1000 0001 15

16. Number Recognition Sub-Networks 16

17. Number Recognition Test Circuit The network contains several levels/layers of hidden operations between input and output. These layers include row detection, number recognition, and encoding. 17

18. M1 M2 M2 M3 M4 Number Recognition Test Circuit Input Matrices for V0-V19: 18

19. Number Recognition Network – Results 00 01 10 11 19

20. Conclusions • A neural nanoelectronics architecture with a low interconnection density, such as cellular neural networks (CNNs) are implemented in analog circuit techniques so that low power applications, such as intelligent sensor pre-processing are preferred applications. • Limitations: • - Small capacitance values required for room- • temperature operation. • - SET weights are hard wired by the use of capacitive • connections, which limits the range of applications. • - The charge sensitivity of the devices also imposes • strong limitations on the allowable electrostatic • interaction between different devices in a ULSI circuit. 20