2004-May-12 JaeYeong Kim

1. Chap. 13 Salicide of TiSi2, CoSi2 and NiSi 2004-May-12 JaeYeong Kim

2. Salicide • What is Salicide? • Self-aligined silicide • Simultaneously form a conducting silicide on gate polysilicon and source/drain regions without any additional masking material and process step • Process sequence Source/Drain implant and RTP anneal • metal film deposition • RTP anneal (1st RTP) to form silicide with high resistance phase • removal unreacted metal film • 2nd RTP at higher temperature to transform the high resistance silicide phase to low resistance silicide phase

3. Salicide • Why Salicide ? • Minimizing RC delays for high speed device operation • Low sheet resistance on gate, source and drain areas • Low contact resistance on source and drain • Minimize source/drain series resistance for drive current • Consideration for Salicide • Keep low sheet resistance and contact resistance • Source/drain junction leakage • Gate to drain/source leakage, isolation leakage

4. Titanium Silicide (TiSi2) • Reaction Kinetics : 2-step formation • 1st step (1st RTP step) • 620~680C in nitrogen for 15~60sec • Transform Ti in contact with Si into the metastable, high-resistivity C-49 phase TiSi2 • Ti + 2Si  TiSi2 (C-49) • Selective etching to remove unreacted Ti • 2nd step (2nd RTP step) : 800C • Lower TiSi2 sheet resistance by transforming the metastable C-49 phase into the low energy, low resistivity orthogonal C-54 phase • TiSi2 (C-49)  TiSi2 (C-54) • C-54 phase is 3~4 times lower than C-49 phase (13~20uΩ-cm vs 60~70uΩ-cm) • Why 2-step RTP ? • To prohibit bridge between gate and source/drain • If high temperature process, then Si can diffuse and TiSi2 can be formed along sidewall. • And if high temperature process above 700C, then Ti can react with sidewall spacer oxide.

5. Titanium Silicide (TiSi2) • Other considerations to prohibit bridge • Cleaning of CFx polymers after dry-etch(CHF3/C2F6 plasma) of sidewall • Polymers enhance lateral Ti-Silicide growth over the sidewall spacer • N2 ambient for 1st RTP • N2 is absorbed at Ti grain boundaries and this stuffs grain boundary diffusion path • Reduce the diffusivity of Si in Ti and suppress the lateral silicide reaction

6. Titanium Silicide (TiSi2) • Narrow line width effect • As line width narrow down, then silicide Rs increase • Narrow lines has less grain boundary triple points which acts as nuclei for C-54 phase transformation • Narrow lines are mixed with C-54 and C-49 phase

7. Titanium Silicide (TiSi2) • Proposed process to mitigate the narrow line width effect in TiSi2 • PAI (Pre-Amorphization implant) • To decrease grain size of TiSi2 C-49 phase • Shallow implant into Si and Polysilicon to amorphize before Ti deposition • Induce smaller C-49 grain size (~0.07um) compared to 0.2um grain size without PAI • PAI can cause junction leakage problem due to implant damage • Mo implant • Ti and Mo-doped polysilicon directly react to form C-54 phase • But Ti and Mo-doped single crystal silicon need to C-49 growth first • Mo implant + PAI • C-54 phase can be achieved by single silicide anneal step

8. Cobalt Silicide (CoSi2) • Process sequence of CoSi2 Salicide : 2 step RTP • Co deposition pre-cleaning • CoSi2 is sensitive to Si surface conditions : native oxide can inhibit silicidation reaction • Generally use diluted HF cleaning and in situ rf-backsputtering to clean Si surface • Co sputter-deposition • Silicon consumption is about 25% greater than TiSi2 formation • (35.9nm of Si is consumed by 10nm of Co to form 35.9nm of CoSi2) • 1st RTP anneal • Co + Si  CoSi (450C) • 2nd RTP anneal CoSi + Si  CoSi2 (700C) • Removal of unreacted Co • Hot H2SO4:H2O2 solution or • NH4OH:H2O2:H2O (SC1) etch followed by HCl:H2O2:H2O (SC2) etch

9. Cobalt Silicide (CoSi2) • Diode leakage issues • Primary cause of leakage : formation of rough interface between Si and CoSi2 • Arise from native oxide or other contamination before Co deposition • Effective cleaning of Si surface before Co sputtering • Dip in dilute HF • In-situ sputtering cleaning before Co sputtering deposition • High temperature 2nd RTP : 800~850C • 450C 1st RTP can cause spike of cobalt silicide in Si substrate • High temperature 2nd RTP can dissolve spike and smooth interface • Enhancement of diffusion kinetics • Increase solubility of Co in Si

10. Cobalt Silicide (CoSi2) • TiN Capping of cobalt-salicide films • Why Ti or TiN capping layer ? • Sensitive to oxidation and contamination due to oxygen and other contamination • Oxidation change the phase-transformation temperature from Co to CoSi2 and higher sheet resistance • In-situ deposition of capping layer is effective approach to control ambient contamination • Advantage • Less line width dependent, low resistance film • Eliminate bridging by reducing lateral growth of CoSi2 • Higher thermal stability in case of Ti capping layer

11. Nickel Silicide (NiSi) • Single RTP step at 400~500C (15~18uΩ-cm2) • Less narrow line width effect • Silicon consumption is only 80% of CoSi2 • Several advantages exist in NiSi • Sentitive to contamination on Si surface • Lead to rough surface and higher diode leakage on shallow junction • TiN capping layer and nitrogen doping reduce diode lekage • Poor thermal stability • Need to prevent transformation to high resistivity NiSi2 phase • Resistivity increased at 600C

12. Nickel Silicide (NiSi)