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Internet Routers

This article explores the functionality of routers and various optimization methods for improved performance. Topics covered include rule tables, longest-prefix matching, power reduction techniques, and trie representations.

hazelrodriguez
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Internet Routers

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  1. Internet Routers http://www.windowsecurity.com/whitepapers/Excerpts_from_The_Encyclopedia_of_Networking_.html

  2. Sample Routers

  3. Router Functionality OUTPUT PORTS INPUT PORTS

  4. Rule Table • Used to decide where to send a packet next (next hop). • Destination address. • Can get larger than 1M rules

  5. Router Rule Table • USA  Output port 1 • Illinois  Port 2 • Chicago  Port 3 • Europe  Port 4 • Asia  Port 5 • Etc.

  6. Router Rules • Range • [35, 2096] • Address/mask pair • 101100/011101 • Matches 101100, 101110, 001100, 001110. • Prefix filter. • Mask has 1s at left and 0s at right. • 101100/110000 = 10* = [32, 47]. • Special case of a range filter.

  7. Example Router Table P1 = 10* P2 = 111* P3 = 11001* P4 = 1* P5 = 0* P6 = 1000* P7 = 100000* P8 = 1000000* P1 matches all addresses that begin with 10.

  8. Tie Breakers • First matching rule. • Highest-priority rule. • Most-specific rule. • [2,4] is more specific than [1,6]. • [4,14] and [6,16] are not comparable. • Longest-prefix rule. • Longest matching-prefix.

  9. Longest-Prefix Matching P1 = 10* P2 = 111* P3 = 11001* P4 = 1* P5 = 0* P6 = 1000* P7 = 100000* P8 = 1000000* Destination = 100000000 P1, P4, P6, P7, P8 match this destination P8 is longest matching prefix

  10. Table Size • 1M+ rules • Prefix up to 32 bits in IPv4 • Prefix up to 128 bits in IPv6 • OC192, 10Gbps 32 mpps (40-byte packets) • Log2 n schemes make too many memory accesses. • 50,000 updates/sec

  11. Control Plane Updates Data Plane Lookups Handling Updates • Batch No lookup delay Rebuild time Time to switch Double resource

  12. Control Plane Updates Data Plane Lookups Handling Updates • Incremental Minimize lookup lockout

  13. Types of Solutions • Hardware • TCAM (Ternary Content Addressable Memory) • Using binary tries for power reduction  • Software • 1-bit and multibit tries  • Compact representation of binary tries • 2-dimensional tries

  14. Ternary CAMs 011* 000* 11* 01* 00* 0* * H7 H6 H5 H4 H3 H2 H1 d = 011001 Longest prefix matching Highest priority matching Insert/Delete Priority Encoder TCAM SRAM

  15. Ternary CAM Limitations • Capacity • Cost • Power • Board space • Scalability to IPv6? • Ranges? • Multidimensional filters?

  16. TCAM Power Reduction 011* 000* 11* 01* 00* 0* * H7 H6 H5 H4 H3 H2 H1 Power proportional to size of TCAM searched n rules  power ~ cn TCAM SRAM

  17. Use an Indexed TCAM H6 H3 000* 00* 0,2 2,3 5,2 00* 0* * H7 H4 H2 011* 01* 0* ITCAM ISRAM H5 H1 11* * DTCAM DSRAM Ideally, |ITCAM| =|each DTAM partition| = sqrt(n) Power ~ 2 sqrt(n)

  18. * 0* 00* 01* 11* 000* 011* Partition Using A Binary Trie 011* 000* 11* 01* 00* 0* * H7 H6 H5 H4 H3 H2 H1 TCAM SRAM

  19. * 0* 00* 01* 11* 000* 011* DTCAM Partitioning H6 H3 000* 00* 0,2 2,3 5,2 00* 0* * H7 H4 H2 011* 01* 0* ITCAM ISRAM H5 H1 11* * DTCAM DSRAM

  20. 1-Bit Trie P1 = 10* P2 = 111* P3 = 11001* P4 = 1* P5 = 0* P6 = 1000* P7 = 100000* P8 = 1000000* P5 P4 P1 P2 P6 P3 P7 P8

  21. Complexity O(W)/operation P5 P4 P1 P2 P6 P3 P7 P8

  22. Batch Updates • Reduce number of memory accesses for a lookup. • Multibit trie.

  23. Multibit Tries • Branching at a node is done using >= 1 bit (rather than exactly 1 bit) • Fixed stride • Nodes on same level use same number of bits • Variable stride

  24. Fixed-Stride Tries • Number of levels = number of distinct prefix lengths. • Use prefix expansion to reduce number of distinct lengths.

  25. Prefix Expansion P1 = 10* P2a = 11100* P2b = 11101* P2c = 11110* P2d = 11111* P3 = 11001* P4a = 11* P5a = 00* P5b= 01* P6a = 10000* P6b = 10001* P7a = 1000001* P8 = 1000000* P1 = 10* P2 = 111* P3 = 11001* P4 = 1* P5 = 0* P6 = 1000* P7 = 100000* P8 = 1000000* #lengths = 7 #lengths = 3

  26. Fixed-Stride Trie 2 P5 P5 P1 P4 3 P6 P6 3 P3 P2 P2 P2 P2 2 P8 P7

  27. P5 P5 P1 P4 P6 P6 P3 P2 P2 P2 P2 P8 P7 Optimization Problem • Find least memory fixed-stride trie whose height is at most k.

  28. P5 P4 2 P5 P5 P1 P4 P1 P2 3 P6 P3 P2 P2 P2 P2 5 P3 P8 P7 P6 P6 P6 P6 P6 P6 . . . P7 P8 Variable-Stride Tries

  29. Binary Tries 011* 000* 11* 01* 00* 0* * H7 H6 H5 H4 H3 H2 H1 H1 H2 H3 H4 H5 H6 H7

  30. 4 bytes/ptr  8 bytes+ per node 48+ bytes Succinct Representation of Tries

  31. a a b b c c d d Succinct Representation of Tries Internal Bit Map (IBM) = 101001001000000 Next Hop List = abcd 15 bits for IBM vs 48 bytes for child pointers Popcount

  32. a b c d Succinct Representation of Tries Shape Bit Map (SBM) = 111101001 Internal Bit Map (IBM) = 101011 Next Hop List = abcd 15 bits for SBM & IBM vs 48 bytes for child pointers

  33. Binary Trie P1 = * P2 = 0* P3 = 000* P4 = 10* P5 = 11* (a) prefixes

  34. Tree Bitmap

  35. Shape Shifting Trie

  36. Hybrid Shape Shifting Trie

  37. Two-Dimensional Filters • Destination-Source pairs. • (0*, 1100*) • Dest address begins with 0 and source with 1100 • Least-cost tie breaker • (0*, 11*, 4) and (00*, 1*, 2) • Packet (00…, 11…) • Use second rule.

  38. 2D 1-Bit Tries • F1 = (0*, 1100*, 1) • F2 = (0*, 1110*, 2) • F3 = (0*, 1111*, 3) • F4 = (000*, 10*, 4) • F5 = (000*, 11*, 5) • F6 = (0001*, 000*), 6) • F7 = (0*, 1*, 7)

  39. 2D Multibit Tries • F1 = (0*, 1100*, 1) • F2 = (0*, 1110*, 2) • F3 = (0*, 1111*, 3) • F4 = (000*, 10*, 4) • F5 = (000*, 11*, 5) • F6 = (0001*, 000*), 6) • F7 = (0*, 1*, 7)

  40. Space-Optimal 2D Multibit Tries • Given k. • Find 2DMT that can be searched with <= k memory accesses and has minimum memory requirement.

  41. 2D Binary Tries • Succinct representations • 2D hybrid shape shifting tries with minimal memory and specified bound on number of memory accesses to do a lookup

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