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V2C DBE and Correlator Meeting @ Wettzel 21th. March, 2009. Current Status of Developments of Digital Backend Systems at NICT Kashima. Atsutoshi Ishii *4,1,5 , Kazuhiro Takefuji *1 , Hiroshi Takeuchi *2 , Moritaka Kimura *1 , Tetsuro Kondo *1,3 and Yasuhiro Koyama *1
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V2C DBE and Correlator Meeting @Wettzel 21th. March, 2009 Current Status of Developments of Digital Backend Systems at NICT Kashima Atsutoshi Ishii *4,1,5 ,Kazuhiro Takefuji *1, Hiroshi Takeuchi*2, Moritaka Kimura *1, Tetsuro Kondo *1,3 and Yasuhiro Koyama *1 *1 National Institute of Information and Communications Technology, Japan *2 ISAS/JAXA *3 Ajou University, Korea *4 Geographical Survey Institute, Japan *5 Advanced Engineering Services Co.,Ltd.
K5 systems Data Acquisition System VSSP:versatile sampling and signal processor VSI:Versatile Scientific Interface or : VLBI standard interface
Block Diagram of ADS3000+ Analog InputDC - 2.5GHz Writable FPGA via Ethernet
Inside ADS3000+ A/D converter 8bit, 2048MHz, 2ch OR 8bit, 4096MHz, 1ch FPGA Xilinx Virtex5 XC5VLX110-3 FPGA Xilinx Virtex5 XC5VLX220-2
ADS3000+ Front Panel LCD display Status LEDs Operation SW Back Panel VSI output x 4 RS232C Ethernet
ADS3000 ADS3000+ • Adopting faster AD sampler chip (e2v EV8AQ160) • Replacing one FPGA with two high performance FPGAs • Rewritable FPGA program through the Ethernet interface • Support multi channel DBBC (digital baseband converter)
4Gsps sampling test Ethernet RF IN ADS3000+ (8bit, 4096MHz, 1ch MODE) From Internal Buffer (1 Mbit ) SG (Signal Generator) CW : 100 – 3000 MHz Step Freq. : 100 MHz
4Gsps sampling test Relative Power [dB] CW Signals from Second Nyquist Zone
Fringe test using ADS3000+ 12, Feb, 2009 ・Station : KASIMA34m – MARBLE1 ・Source : 3C84, TaurusA ・Frequency : 8192 ‐ 8630 MHz ( Band width 438MHz) ・Sampling rate : 2048 MHz, 1bit
Fringe test using ADS3000+ KASHIMA34m ADS3000+ K5/VSI Recorder MARBLE 1
First Fringes using ADS3000+ Consistent with a priori 3C84 Consistent with a priori TauA It was confirmed that data was acquired with coherence had been maintained.
Summary • Latest sampler ADS3000 + is under development. • The fringe test using ADS3000+ has succeeded. • Future task for ADS3000+ development • Programming of FPGA for DBBC. • Plan to Equip with 10 Gigabit Ethernet and USB 3.0 IF.
DBBC Diagram of ADS3000+ Filter coefficient memory Parameter • Frequency can be obtained flexibly • by a tunable NCO(numerically controlled oscillator) • Bandwidth is selectable 2, 4, 8, 16 MHz