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Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, Patrick Palmer

A 3GHz Switching DC-DC Converter Using Clock-Tree Charge-Recycling in 90nm CMOS with Integrated Output Filter. Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, Patrick Palmer University of British Columbia (UBC) Vancouver, BC, Canada. Motivation.

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Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, Patrick Palmer

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  1. A 3GHz Switching DC-DC ConverterUsing Clock-Tree Charge-Recycling in 90nm CMOS with Integrated Output Filter Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, Patrick Palmer University of British Columbia (UBC) Vancouver, BC, Canada

  2. Motivation • Power-limited CPU performance • Trend: > 4 CPU cores on one chip • Solution? • Dynamic Voltage and Frequency Scaling (DVFS) - Each core scaled differently based on load • Need multiple supply voltages on-chip

  3. Motivation • How to supply multiple voltages? Our approach … • Global voltage distribution (high Vdd) • Local voltage regulation(on-chip, low Vdd) Support for … • Coarse-grain voltage islands (e.g., CPU cores) • Fine-grain voltage islands (e.g., ALU, FPU, …)  On-chip “local” voltage regulation

  4. Problem Definition • On-chip “local” voltage regulation • Constraints • On-chip components, “standard” CMOS • Scaled down voltage buck converters • Shrink L, C to fit on-chip • Efficiency trade-off • Local regulator consumes power • Local regulator saves power by DVFS  consumption < savings 

  5. Summary Results • On-chip DC-DC buck (step-down) converter • Standard 90nm CMOS • 1V input, 0.5~0.7V output, 100mA • Up to 158%effective efficiency • Over 100% !!!??? • By recycling chargethrown away in clock tree • High-speed operation • 3GHz CPU clock  3GHz buck converter • Monolithic L and C (converter area 0.27mm2) • Unique ZVS delay circuit improves efficiency

  6. Switch Mode Power Supply • CMOS inverter as power switches in buck converter

  7. Clock and SMPS Merging • CPU clock: 3GHz clock and large Cclk • SMPS: large Mp, Mndrive chain

  8. Clock and SMPS Merging • Combine the driver circuits

  9. Key Contribution: CHARGE RECYCLING • Benefits • Shared driver chain • Cclk added to SMPS • Note: NMOS drains Cclk, wastes charge! • Delaying NMOS  ZVS recycles clock charge!

  10. ZVS Detailed Operation • ZVS delay circuit D • Delay only rising edge of Vn • Implemented inside the clock chain

  11. ZVS Detailed Operation (Mode 1) • Mode 1 (0 < t < DTsw) • Mp is ON • Current builds up in the inductor • Cclk charges up D = Duty cycle Tsw = Switching period

  12. ZVS Detailed Operation (Mode 2) • Mode 2 (DTsw < t < DTsw+Tzvs) • Both power transistors are OFF • Inductor current discharges Cclk • Cclk charge is recycled to output load D = Duty cycle Tsw = Period Tzvs = ZVS delay

  13. ZVS Detailed Operation(Mode 3) • Mode 3 (DTsw+Tzvs < t < Tsw) • Mnturns ON when Vclk 0 • ZVS for Mn • Inductor current decreases linearly D = Duty cycle Tsw = Period Tzvs = ZVS delay

  14. Detailed Operation • ZVS delay circuit for Mn • Delay rising edge of Vn

  15. Detailed Operation • Adaptive ZVS delay circuit for Mn • Falling edges of Vp and Vn are synchronized

  16. Implementation • Chip 1mm2, converter 0.27mm2

  17. Implementation Reference clock circuit Circuit 2, Pin2 Combined SMPS + clock circuit Circuit 1, Pin1, Pout1 • Charge recycling of the clock tree capacitor

  18. Power Conversion Efficiency Efficiency (effective) Efficiency (raw) • Pout1 = output power (delivered to load) • Pin1 – Pin2 = incremental power to operate SMPS only Pin1 = power of combined SMPS + clock circuit Pin2 = power of referenceclock circuit

  19. Comparative Results

  20. Contributions • Key concepts • High switching frequency saves area • Combined driverssaves area and switching loss • Recycled charge converter load discharges Cclk • Unique ZVS delay circuit lower power loss • Limitations • Regulation needs variable duty cycle clock • May introduce additional clock jitter • Mostly suitable for edge-triggered blocks (no latches)

  21. References [JSSC05] P. Hazucha, G. Schrom, H. Jaehong, B. A. Bloechel, P. Hack, G. E. Dermer, S. Narendra, D. Gardner, T. Karnik, V. De, and S. Borkar, “A 233MHz 80%-87% Efficient Four-Phase DC-DC Converter Utilizing Air-Core Inductors on Package,” IEEE J. Solid-State Circuits, vol. 40, pp. 838-845, Apr., 2005. [ISSCC06] S. Abedinpour, B. Bakkaloglu, and S. Kiaei, “A Multi-Stage Interleaved Synchronous Buck Converter with Integrated Output Filter in a 0.18µm SiGe Process,” ISSCC Dig. Tech. Papers, pp. 356-357, Feb., 2006.

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