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Defect-tolerant FPGA Switch Block and Connection Block with Fine-grain Redundancy for Yield Enhancement. Anthony J. Yu Guy G.F. Lemieux August 25, 2005. Outline. Introduction and Motivation Previous Approaches Fine-grain Redundancy Results Conclusions. Introduction and Motivation.
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Defect-tolerant FPGASwitch Block and Connection Block with Fine-grain Redundancy for Yield Enhancement Anthony J. Yu Guy G.F. Lemieux August 25, 2005
Outline • Introduction and Motivation • Previous Approaches • Fine-grain Redundancy • Results • Conclusions FPL'05 - Presentation
Introduction and Motivation • Scaling introduces new typesof defects • Smaller feature sizes susceptible to smaller defects • Expected results • Defects per chip increases • Chip yield declines • FPGAs are mostly interconnect • FPGAs must tolerate multiple interconnect defects to improve yield (and $$$) FPL'05 - Presentation
General Defect Tolerant Techniques • Defect-tolerant techniques minimize impact (cost) of manufacturing defects • FPGA defect-tolerance can be loosely categorized into three classes: • Software Redundancy – use CAD tools to map around the defects • Hardware Redundancy – incorporate spare resources to assist in defect correction (eg. Spare row/column) • Run-time Redundancy – protection against transient faults such as SEUs (eg. TMR) FPL'05 - Presentation
Previous work – 1 – Xilinx • Xilinx’s Defect-Tolerant Approach • Customer (knowingly) purchases “less that perfect” parts • Customer gives Xilinx configuration bitstream • Xilinx tests FPGA devices against bitstream • Sells FPGA parts that “appear” perfect • Defects avoid the bitstream • Limitation: • Chips work only with given bitstream – no changes! FPL'05 - Presentation
Previous work – 2 – Altera • Altera’s Defect-Tolerant Approach • Customer purchases “seemingly perfect” parts • Make defective resources inaccessible to user • Coarse-grain architecture • Spare row and column in array (like memories) • Defective row/column must be bypassed • Use the spare row/column instead • Limitation: • Does not scale well (multiple defects) FPL'05 - Presentation
Objective • Problem • FPGA yield is on decline because of aggressive technology scaling • Proposed Solution • Defect-tolerance through redundancy • Important Objectives • Interconnect defects important (dominates area) • Tolerate multiple defects (future trend) • Preserve timing (no timing re-verification) • Fast correction time (production use) FPL'05 - Presentation
Our Proposed SolutionFine-grain Redundancy (FGR) – Defect Avoidance by Shifting FPL'05 - Presentation
Island-style FPGA FPL'05 - Presentation
Directional Switch Block FPL'05 - Presentation
Directional Switch Block FPL'05 - Presentation
Defect-tolerant Switch Block FPL'05 - Presentation
HSPICE Schematic FPL'05 - Presentation
Switch Implementation Options • Several detailed implementations are possible • Trade off area / delay / yield(repairability) FPL'05 - Presentation
Defect Avoidance –Switch Implementation Option 1 Can avoid contention by pre-shifting the red signal… OR… [ lower area overhead, lower yield improvement ] FPL'05 - Presentation
Defect Avoidance –Switch Implementation Option 2 …OR … can avoid contention by embedding the IMUX [ higher area overhead, best yield ] FPL'05 - Presentation
Results • Area • Delay • Area Delay Product • Yield • Summary FPL'05 - Presentation
Area Results FPL'05 - Presentation
Delay Results FPL'05 - Presentation
Area-Delay Product FPL'05 - Presentation
Yield – 1Switch Implementation Affects Yield * Assumes all bridging defects FPL'05 - Presentation
Yield – 2Larger Arrays Tolerate More Defects FPL'05 - Presentation
Summary FPL'05 - Presentation
Conclusions • FGR meets desired objectives • Tolerates multiple randomly distributed defects • Defect correction does not perturb timing • Tolerates an increasing number of defects as array size increases • Correction can be applied quickly • FGR has different implementation options • Trade-offs between yield, area and delay can be made • Best Area: EN11 • Best Delay: EM11 • Best Yield: EM22 FPL'05 - Presentation
Thank you! anthonyy@ece.ubc.ca
Single-length Defects FPL'05 - Presentation
Double-length Defects FPL'05 - Presentation
Minimum Fault-free Radius (MFFR) FPL'05 - Presentation