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Cluster Block Status Report

This report provides an overview of the latest developments in firmware development and testing for new CDT modules, including the installation and testing tasks remaining in J-PARC. It also covers collaboration details and new blocks inside the master firmware, addressing protocol finalization and cluster block timing. The simulation examples for cluster bit blocks and detailed timing information are included for reference. Stay updated with the progress and upcoming tasks with this comprehensive report.

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Cluster Block Status Report

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  1. Cluster Block Status Report Mircea Bogan Chicago, 2/23/2017

  2. Cluster Block Status Report Manufactured 25 new CDT Modules Tested new Modules (Yuting) Developed Firmware for CDT: - CDT Block inside ADC - Firmware for CDT Modules (Yu-Chen)

  3. Cluster Block Status Report To Do in J-PARC: - Install new CDT Modules - Test Fan-Out Function - Test Cluster Bit Function

  4. Collaboration: New Blocks inside Master Firmware: - Generation of pL1 pulse - Management of pL1A pulse - Receipt of Cluster Numbers. Need to finalize protocol: Cluster Numbers or Yes/No. Testing of CB/Master Handshake

  5. Cluster Block Timing pL1A L1A 0 63 ADC[13:0] ADC[13:0] Delayed Samples 0 to 63 - Cluster Bit Samples 0 to 63 - Cluster Map ~ 500 clocks Cluster Bits are calculated every 8 ns. The pL1A pulse latches the Cluster Bits corresponding to the same 64 samples that stand to produce the L1A pulse.

  6. Full Cluster Block Simulation tmin=43, tmax=43 CB Delayed CB pL1A pulse that latches CB Peak Cluster Bits are delayed. The pL1A pulse that latches the CBs comes 150 clocks after Sample43

  7. Full Cluster Block Simulation - Detail tmin=43, tmax=43 pL1A CB-[15:0] CB-3 CB-15 CB-2 CB-1 CB-8 CB-12 CB-0 CB-4 LVDS Serial Data Out The pL1A pulse that latches delayed CBs comes 135-150 clocks after Sample43 One 8-Bit Bus is passed to ALTLVDS. There are 4 successive 8-BIT Words for each trigger: [7]= Data Valid; [6]=4-BIT Counter; [5:4]=8-BIT VME_Word; [3:0]=16 Cluster Bits.

  8. Cluster Block Simulation Examples Backup Slides

  9. Cluster Bit Block (CBB) Simulation Examples - A tmin=22, tmax=43 22 Samples for Cluster Bit (CB) A CB-A For CB-A, Peak is Sample 22 (The first sample in the set) CBB looks at 22 successive samples [22,…,43] and presents a Cluster Bit after 7 clocks. Peak = Max Sample Value; tpeak = Time of Max Sample CB = 1 if Peak > [ped(9..0) + thresh(9..0)] and tmin<tpeak<tmax Time of each Cluster Bit: tCB = tLast_sample + 56ns. tmin and tmax can be set between 22 and 43. In Example above, we have 22 successive CB=1 for one Peak.

  10. CBB Simulation Examples - B tmin=27, tmax=37 22 Samples for Cluster Bit B Cluster Bit B Peak is Sample 27 In this example, tmin = 27 and tmax =37, so we have 11 successive CB=1 for one Peak.

  11. CBB Simulation Examples – C, D, E tmin= tmax= 22 22 Samples for Cluster Bit C Cluster Bit C Peak is Sample 22 tmin= tmax= 24 22 Samples for Cluster Bit D Cluster Bit D Peak is Sample 24 tmin= tmax= 43 Cluster Bit E Peak is Sample 43 22 Samples for Cluster Bit E If tmin = tmax = tm => Only one CB=1. tCB=1 = tpeak + 56ns + (43 – tm)*8ns Delay from Peak Moment CB=1 Moment

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