Von Neumann Model Con’d. Assembly Intro

1. Von Neumann Model Con’d.Assembly Intro COMP5201 Revision: 1.2 Date: June 18, 2003 Serguei A. Mokhov, mokhov@cs.concordia.ca

2. Contents • System Bus • Layers of Abstraction • Logic Gates: IC Building Blocks • CPU Internals • Instruction Fetch-Execute Cycle • Glimpses of Assembly and Sample Programs Serguei A. Mokhov, mokhov@cs.concordia.ca

3. System Bus • Von Neumann: how does the computer components communicate? Answer: via the System Bus. • An external (to the CPU) mean of communication between the CPU and other computer components. • NOTE: there is also an internal bus within the CPU that connects its registers, ALU and CU – do NOT mix it with the System Bus, please! Serguei A. Mokhov, mokhov@cs.concordia.ca

4. System Bus (2) • System Bus can often be seen as three “sub-busses”: • Data Bus. Primarily for data-only communication among different types of units, such as CPU, Memory, and I/O devices. • Address Bus. Used to communicate address information, i.e. where to look for/to send to the data (an address in the Memory; I/O device number). • Control Bus. Control data lines to report status, to request writing or reading between communicating parties Serguei A. Mokhov, mokhov@cs.concordia.ca

5. System Bus (3) CPU Memory I/O Device • NOTE: The three sub-busses may not necessarily be implemented as different IC chips. It is conceivable to have a system-on-a-chip, in which case, the chip interface is used to connect to other transducers/components. Data Bus Address Bus Control Bus System Bus Serguei A. Mokhov, mokhov@cs.concordia.ca

6. Layers of Abstraction • A computer system can be examined at various levels of abstraction. At a higher level of abstraction, fewer details of the lower levels are observed. • Instead, new (functional) details may be implemented at that level of abstraction. • Each level of abstraction provides a set of building blocks using which the next higher level of abstraction can be constructed, with more functionality. • This principle of information hiding is important in system design, as it enhances modularity, correctness, security, and usability of a system. Serguei A. Mokhov, mokhov@cs.concordia.ca

7. Levels of Abstraction Serguei A. Mokhov, mokhov@cs.concordia.ca

8. Levels of Abstraction (2) • In this course, we will focus on the assembler level of abstraction of a computer system with a fair amount of attention to its neighbor levels below and above. • A major difference between an assembly language user (programmer) and a user at higher levels is the amount of hardware details made available to the former. • These hardware details enable the former to directly manipulate program design for performance or real-time needs. Serguei A. Mokhov, mokhov@cs.concordia.ca

9. IC Building Blocks • A MOS Transistor and Capacitor • Technology Innovation: • Scaling from 103 to 109 devices in a single chip • Consequence: • Memory size increase  cheaper • Functionality improvements/additions • Speed increase Serguei A. Mokhov, mokhov@cs.concordia.ca

10. MOS Transistor: Logic Source Source Source Gate Drain Drain Drain 0 1 Low voltage at the gate High voltage at the gate Serguei A. Mokhov, mokhov@cs.concordia.ca

11. Capacitor: Memory Serguei A. Mokhov, mokhov@cs.concordia.ca

12. Not-And  NAND Not-Or  NOR NAND and NOR gates are an universal gates to implement any complex function in hardware. Hierarchically used inside an integrated circuit (IC) chip. NAND and NOR Gates Logic 1 - High voltage A B X ------- 0 0 1 0 1 0 1 0 0 1 1 0 A B X ------- 0 0 1 0 1 1 1 0 1 1 1 0 A B A NOR B A NAND B X X = A NAND B = NOT (A AND B) X = A NOR B = NOT (A OR B) Serguei A. Mokhov, mokhov@cs.concordia.ca

13. NAND: Question • Why NAND (and also NOR) gates are so universal compared to AND, OR, NOT, and XOR gates? • What’s so good about them (besides the universality)? Serguei A. Mokhov, mokhov@cs.concordia.ca

14. Registers CPU Internals Control Unit Internal Bus ALU CPU Serguei A. Mokhov, mokhov@cs.concordia.ca

15. CPU: Registers • A register is a unit of storage inside a CPU, holding temporary program data/instruction to be used in program execution. • Two types of registers: general purpose (GPS) and special purpose registers (GPR). • A general-purpose register is for general use in programming • E.g.: storage of arguments • A special-purpose register has specifically assigned function • E.g.: accumulator, stack pointer (SP), program counter (PC) • They are there to provide local storage inside a processor, making program information locally accessible and hence faster accesses. [Recall the Principle of Locality to enhance system performance] Serguei A. Mokhov, mokhov@cs.concordia.ca

16. CPU: Control Unit • It is the “brain” or “coordinator” of the ISP (instruction set processor) as it ensures that the processor will behave exactly as defined by its instruction set. • Under the Von Neumann model, the processor • repeatedly fetches an instruction from the memory, • interprets its functionality, and • executes it. • This activity is carried out in an Instruction Fetch/Execute Cycle and is repeated once the system power is turned on. Serguei A. Mokhov, mokhov@cs.concordia.ca

17. Instruction Fetch-Execute Cycle • May simply be referred to as • Fetch-Execute Cycle • Instruction Cycle • Basic F/E cycle involves: • Fetching the next instruction from the memory (“next” identified by a some kind of special pointer to some memory location) • Bringing the instruction is brought to the CPU and interpreted (decoded) • Fetching the instruction arguments (data) from either registers or other memory locations if needed • Executing the instruction and producing the result, if applicable • Storing back the result (if any; to either memory or registers) Serguei A. Mokhov, mokhov@cs.concordia.ca

18. Program Counter • The existence of the (next) instruction pointer, also often known as, Program Counter, or PC,is a key feature in the Von Neumann model that forms the basis of more than 99% of computers ever built. • Under this model, a program adopts a sequential semantics: program instructions are “assumed” to be executed atomically in program (sequential) order. • What would be an alternative, the remaining 1%? Serguei A. Mokhov, mokhov@cs.concordia.ca

19. inst1: mov ax, A ; move data from ; memory location A ; to register ax inst2: add ax, bx ; add register bx ; to register ax Example • Processor fetches and executes inst1; then repeats the same for inst2 • Notice inst1 and inst2 are stored in consecutive memory locations • Suppose initially the memory location A contains 24 and the register bx contains 12 • After executing inst1, ax will contain 24 • Then, after executing inst2, ax will contain 36 Serguei A. Mokhov, mokhov@cs.concordia.ca

20. Observations • An instruction has: • An opcode (operation code), such as mov or add (human-readable or their binary equivalents) • Operand(s) – arguments to the instruction. Represent data for the instruction to work with pointed by/contained in either a register or a memory location • In the example, there are two operand addresses. Sometimes, machines like these are called 2-address machines. Obviously, there are other possibilities, such as 3-address machines[example: add a, b, c] Serguei A. Mokhov, mokhov@cs.concordia.ca

21. MASM: Sample Programs • See: • hworld.asm – Hello World • reverse.asm – Displays reversed input Serguei A. Mokhov, mokhov@cs.concordia.ca