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Presenter: Chien-Chih Chen

National Sun Yat-sen University Embedded System Laboratory A Software-Based Test Methodology for Direct-Mapped Data Cache. Presenter: Chien-Chih Chen. Yi-Cheng Lin 17 th Asian Test Symposium, 2008. Abstract.

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Presenter: Chien-Chih Chen

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  1. National Sun Yat-sen University Embedded System LaboratoryA Software-Based Test Methodology for Direct-Mapped Data Cache Presenter: Chien-Chih Chen Yi-Cheng Lin 17th Asian Test Symposium, 2008.

  2. Abstract We present a software-based test methodology that utilizes an on-chip processor to perform test procedures for direct-mapped data cache. The cache system under test is divided into two major groups, namely the memory modules and the logic modules. For the memory modules which include the tag memory, the data memory, and the physical address tag memory, systematic procedures to transform a widely-used March algorithm into various executable instruction sequences are developed. For the logic modules, extensive analysis on the functions as well as the structures (architecture, RTL, and gate-level) of these modules is carried out and effective test instruction sequences based on the analysis are derived. A 100% fault coverage for six conventional RAM fault models and 99.13% test efficiency for single stuck-at fault model are obtained on a real 32-bit RISC processor. These results validate the viability and effectiveness of the proposed methodology for data cache testing.

  3. Related Works Functional fault models and test sequences [5] March C- algorithm for memory module test [4] Transform March algorithm into pseudo-instruction sequences [7] Extend the functional test to various cache organizations [6] Software-based test methodology for direct-mapped cache

  4. What’s the Problem ? • Area, timing and power consumption • Scan-cell insertion, built-in self-test (BIST) [1] – [3] • No fault coverage is calculated • Focus on functional fault [5] – [7]

  5. Direct-Mapped Data Cache • Memory modules • Tag Unit • Data Unit • Physical Address Tag Unit • Logic modules • Controller • Comparator • Valid Unit • Dirty Unit • Multiplexer

  6. March C- Algorithm • March C- {⇕(w0);⇑(r0,w1);⇑(r1,w0);⇓(r0,w1);⇓(r1,w0);⇕(r0)} • ⇑: up addressing order, 0 to n-1 • ⇓: down addressing order, n-1 to 0 • ⇕: either way • r0: read 0 from memory • w0: write 0 to memory • RAM faults detection • Stuck-at-fault (SAF) • Transition fault (TF) • Address decoder fault (AF) • Coupling fault (CF)

  7. Software-Based Test Sequence • Pseudo Test Instruction • R ([T,i,x], D) ; R ([T,i,x], D) ; W ([T,i,x], D) ; W([T,i,x], D) ; RM ([T,i,x], D) ; WM ([T,i,x], D) ; INVi ; CLEARi ; EC ; DC • Pseudo Test Sequences (Ex: stuck-at-1 fault on valid bit) • Initialization phase • Data setting phase R ([T,i,x], D), INVi, DC, WM ([T,i,x], !D) • Function execution phase EC, R ([T,i,x], !D) • Result checking phase D: load from cache, INVi instruction do not take effect

  8. Test Sequence for Memory Modules • The March sequence for data RAM • The March sequence for tag RAM • The March sequence for PA tag RAM

  9. Test Sequence for Logic Modules • Multiplexer • R ([T,i,xn], Wn) ; R ([T,i,xn], Wn) • Dirty unit • R ([T,i,x], D) ; W ([T,i,x], D) ; DC ; WM ([T,i,x], !D) ; EC ; R ([T’,i,x], !D) • Tag address comparator • Input pairs (A,B): fed netlist of module to ATPG • R ([An,i,x], D) ; R ([Bn,i,x], !D) for a cache miss • R ([An,i,x], D) ; R ([An,i,x], D) for a cache hit

  10. Test Sequence for Logic Modules (Cont.) • Cache controller

  11. Example of Assembly code

  12. Experimental Results • Environment setup • ADS v1.2: assemble the test code • Cadence Verilog-XL: capture stilumi for test analysis • Design compiler: synthesize Linux-verified ARM-compatible processor with the target direct-mapped cache • RAMSES simulator: run the RAM fault simulation • SyntestTurboscan: run the logic fault simulation • Test results for memory modules • 100% RAM fault coverage • Effectively detect all SAF, TF, AF, CFst, CFin, and CFid faults

  13. Experimental Results (Cont.) • Test Results for logic modules • Statistics of test program • Program size < 30 KB • Execution time < 1 million cycles • Memory requirement < 150 KB

  14. Conclusions • High-performance software-based testing methodology for a direct-mapped data cache • The transformed March test program can detect all commonly used RAM faults • 99.13 % test efficiency for logic modules

  15. Comments • Code sequences for cache functional model verification

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