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Modes of Operation of Block Ciphers in FPGA and ASIC Design with VHDL

Explore block vs stream ciphers, ECB, CTR, CFB, CBC modes in block ciphers, AES encryption/decryption, key generation, and interfaces. Dive into VHDL designs and examples.

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Modes of Operation of Block Ciphers in FPGA and ASIC Design with VHDL

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  1. Lecture 5 Block Diagrams Modes of Operation of Block Ciphers

  2. Modes of Operation of Block Ciphers ECE 448 – FPGA and ASIC Design with VHDL

  3. Block vs. stream ciphers M1, M2, …, Mn m1, m2, …, mn Internal state - IS Block cipher K K Stream cipher C1, C2, …, Cn c1, c2, …, cn Ci=fK(Mi) ci = fK(mi, ISi) ISi+1=gK(mi, ISi) Every block of ciphertext is a function of the current block of plaintext and the current internal state of the cipher Every block of ciphertext is a function of only one corresponding blockof plaintext

  4. Typical stream cipher Sender Receiver initialization vector (seed) initialization vector (seed) key key Pseudorandom Key Generator Pseudorandom Key Generator keystream ki keystream ki mi ci ci mi plaintext ciphertext ciphertext plaintext

  5. Standard modes of operation of block ciphers Block cipher turned into a stream ciphers Block cipher ECB mode Counter mode CFB mode CBC mode

  6. ECB (Electronic CodeBook) mode

  7. Electronic CodeBook Mode – ECB Encryption K K K K M3 M1 M2 MN MN-1 K E E E E E . . . C3 C1 C2 CN CN-1 Ci = EK(Mi) for i=1..N

  8. Electronic CodeBook Mode – ECB Decryption K K K K C3 C1 C2 CN CN-1 K D D D D D . . . M3 M1 M2 MN MN-1 Mi = DK(Ci) for i=1..N

  9. Electronic CodeBook Mode – ECB (simplified block diagram) Mi Ci Ci = EK(Mi) Mi = DK(Ci) IN IN K K E D OUT OUT Ci Mi

  10. Electronic CodeBook Mode – ECB (combined block diagram) bdi IN IN K K E D OUT OUT bdi = Mi for Encryption Ci for Decryption bdo bdo = Ci for Encryption Mi for Decryption

  11. Counter Mode

  12. Counter Mode - CTR Encryption K K K K IV+N-1 IV+N-2 IV IV+1 IV+2 . . . K E E E E E . . . kN kN-1 k2 k3 k1 mN mN-1 m2 m3 m1 c2 cN-1 c3 cN c1 ci = mi ki ki = EK(IV+i-1) for i=1..N

  13. Counter Mode - CTR Decryption K K K K IV+N-1 IV+N-2 IV IV+1 IV+2 . . . K E E E E E . . . kN kN-1 k2 k3 k1 cN cN-1 c2 c3 c1 m2 mN-1 m3 mN m1 mi = ci ki ki = EK(IV+i-1) for i=1..N

  14. Counter Mode – CTR (simplified block diagram) IV IV IS1 = IV ci = EK(ISi)  mi ISi+1 = ISi+1 IS1 = IV mi = EK(ISi)  ci ISi+1 = ISi+1 counter counter ISi ISi IN IN K K E E OUT OUT ci ci mi mi

  15. Counter Mode – CTR (combined block diagram) IV bdi = mi for Encryption ci for Decryption counter ISi IN bdo = ci for Encryption mi for Decryption K E OUT bdo bdi

  16. CFB (Cipher FeedBack) Mode

  17. Cipher Feedback Mode - CFB Encryption IV . . . E E E E E . . . k3 kN k1 k2 kN-1 mN mN-1 m3 m1 m2 c2 cN-1 c3 cN c1 ci = mi ki ki =EK(ci-1) for i=1..N, and c0 = IV

  18. Cipher Feedback Mode - CFB Decryption IV . . . E E E E E . . . k3 kN k1 k2 kN-1 mN mN-1 m3 m1 m2 c2 cN-1 c3 cN c1 mi = ci ki ki =EK(ci-1) for i=1..N, and c0 = IV

  19. Cipher Feedback Mode – CFB (simplified block diagram) IV IV register IS1 = IV ci = EK(ISi)  mi ISi+1 = ci register ISi ISi IN IN K K E E IS1 = IV mi = EK(ISi)  ci ISi+1 = ci OUT OUT ci ci mi mi

  20. Cipher Feedback Mode – CFB (combined block diagram) IV bdi = mi for Encryption ci for Decryption register ISi bdi IN bdo = ci for Encryption mi for Decryption K E OUT bdo bdi

  21. CBC (Cipher Block Chaining) Mode

  22. Cipher Block Chaining Mode - CBC Encryption m3 m1 m2 mN mN-1 . . . IV E E E E E . . . cN c1 cN-1 c2 c3 ci = EK(mi ci-1) for i=1..Nc0=IV

  23. Cipher Block Chaining Mode - CBC Decryption cN c1 cN-1 c2 c3 D D D D D . . . . . . IV m3 m1 m2 mN mN-1 mi = DK(ci)  ci-1for i=1..Nc0=IV

  24. Cipher Block Chaining Mode – CBC (simplified block diagram) IV IN register K IS1 = IV ci = EK(ISi  mi) ISi+1 = ci IS1 = IV mi = DK(ci)  ISi ISi+1 = ci D ISi mi OUT IN mi K E ISi register OUT ci ci IV

  25. Cipher Block Chaining Mode – CBC (combined block diagram) bdi IV ci IN K D register bdi ISi OUT bdi IN K E OUT bdo

  26. Advanced Encryption Standard (AES) Pseudocode ECE 448 – FPGA and ASIC Design with VHDL

  27. AES Encryption

  28. AES Decryption

  29. AES: Symbols, Block Diagrams, Interfaces ECE 448 – FPGA and ASIC Design with VHDL

  30. AES_Enc • Encryption Only • Key scheduling done as a part of initialization

  31. Symbol

  32. Block Diagram – AES_Enc

  33. Block Diagram – Round

  34. Block Diagram – KeyUpdate

  35. AES_Enc: Interface with the Division into the Datapath and Controller

  36. AES_Enc_KOF • Encryption Only • Key scheduling done On the Fly

  37. Symbol

  38. Block Diagram – AES_Enc_KOF

  39. Block Diagram – Round

  40. Block Diagram – KeyUpdate

  41. AES_Enc_KOF: Interface with the Division into the Datapath and Controller

  42. AES_EncDec • Encryption and Decryption • Key scheduling done as a part of initialization

  43. Symbol

  44. Block Diagram – AES_EncDec

  45. Block Diagram – Round

  46. Block Diagram – InvRound

  47. Block Diagram – KeyUpdate

  48. AES_EncDec: Interface with the Division into the Datapath and Controller

  49. Example of a Hierarchical Block Diagram JH hash function ECE 448 – FPGA and ASIC Design with VHDL

  50. Top Level

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