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CS 140L Lecture 8 System Design

This lecture provides an overview of the system design for a 4-bit data path control subsystem using three instruction bits and four data bits. The instruction set includes initialization, data movement, storage, addition, shifting, comparison, and bitwise AND operations.

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CS 140L Lecture 8 System Design

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  1. CS 140L Lecture 8System Design Professor CK Cheng CSE Dept. UC San Diego

  2. Lab4. System Design R1 Output Inst(Data) R3 R2 Data Path Control Subsystem

  3. Instruction Set Three instruction bits and 4 data bits.

  4. Instruction Set • Init: R1 = R2 = R3 = (0,0,0,0) • Initialize all three registers to 0 • Mov1: R1 = (D3, D2, D1, D0) • Move data D3-0 to R1 • Mov2: R2 = (D3, D2, D1, D0) • Move data D3-0 to R2 • Store: R2 <= R3 • Store data into R2 from R3 • Add: R3 <= R1 + R2, Overflow flag • Add R1 and R2 and store the sum in R3 • Shift: R3 <= (R2 Shift left by (D3, D2) bits) • Shift R2 by D3-2 bits and store the result in R3 • Comp: flag(R1, R2) <= 1 iff R1>R2 • Compare R1 and R2 and set flag=1 if R1 is bigger • And: R3 <= (R1)&(R2) • AND bitwise R1 and R2. Store the result in R3

  5. Overview of System Design Data Input D3-0 Data output D0 Data Subsystem D1 D2 Control Signals D3 Conditions I0 Control Input I2-0, D3-2 I1 Control Subsystem I2 Control output

  6. Data Path Subsystem overflow Flag 0 1 D3-0 R1 + S5 clk En1 CLR << R2 0 1 0 1 2 3 clk Data R3 S4 S3 S0 En2 CLR Comp CLR En3 S1 S2 &

  7. Control Subsystem D2 CLR D3 En1 I0 En2 I1 Control Subsystem En3 I2 S0 S1 S2 S3 S4 S5

  8. Control Subsystem overflow 0 1 Flag S5 D3-0 R1 + clk CLR En1 0 1 << 0 1 2 3 R2 Data clk S4 S3 R3 S0 CLR En2 Comp CLR En3 S1 S2 & 8

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