Unit 12 Registers and Counters

1. Unit 12Registers and Counters Ku-Yaw Chang canseco@mail.dyu.edu.tw Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

2. Outline 12.1 Registers and Register Transfers 12.2 Shift Registers 12.3 Design of Binary Counters 12.4 Counters for Other Sequences 12.5 Counter Design Using S-R and J-K Flip-Flops 12.6 Derivation of Flip-Flop Input Equations -- Summary Registers and Counters

3. Shift Registers • A shift register • Store binary data • The data can be shifted to the left or right • Bits shifted out one end • May be lost • May be shifted back in the other end Registers and Counters

4. Right-Shift Register Registers and Counters

5. 8-Bit Serial-in, Serial-outShift Register Registers and Counters

6. Timing Diagram for Shift Register Registers and Counters

7. Parallel-in, Parallel-outRight Shift Register Registers and Counters

8. Shift Register Operation Registers and Counters

9. Next-state Equations Q3+ = Sh’ · L’ · Q3 + Sh’ · L · D3 + Sh · SI Q2+ = Sh’ · L’ · Q2 + Sh’ · L · D2 + Sh · Q2 Q1+ = Sh’ · L’ · Q1 + Sh’ · L · D1 + Sh · Q1 Q0+ = Sh’ · L’ · Q0 + Sh’ · L · D0 + Sh · Q0 Registers and Counters

10. Timing Diagram for Shift Register Registers and Counters

11. Shift Register withInverted Feedback Registers and Counters

12. Outline 12.1 Registers and Register Transfers 12.2 Shift Registers 12.3 Design of Binary Counters 12.4 Counters for Other Sequences 12.5 Counter Design Using S-R and J-K Flip-Flops 12.6 Derivation of Flip-Flop Input Equations -- Summary Registers and Counters

13. Binary Counters • Synchronous counters • Synchronized by a common clock pulse • State changes simultaneously • Ripple counters • The state change of one flip-flop triggers the next flip-flop in line. • Not discussed in this text Registers and Counters

14. Synchronous Binary Counter • Using Three T flip-flops Registers and Counters

15. Synchronous Binary Counter • The state of the counter is 011 • Flip-flop C is in state 0 • Flip-flop B is in state 1 • Flip-flop A is in state 1 • Initially, assume that all flip-flops are set to 0 state. Registers and Counters

16. Synchronous Binary Counter • Initially 0 0 0 0 0 0 0 Registers and Counters

17. Synchronous Binary Counter • 1st clock pulse 0 0 1 0 1 1 0 Registers and Counters

18. Synchronous Binary Counter • 2nd clock pulse 0 1 0 0 0 0 1 Registers and Counters

19. Synchronous Binary Counter • 3rd clock pulse 0 1 1 1 1 1 1 Registers and Counters

20. Synchronous Binary Counter • 4th clock pulse 1 0 0 0 0 0 0 Registers and Counters

21. Synchronous Binary Counter • The sequence of flip-flop states in CBA = 000, 001, 010, 011, 100, 101, 110, 111, 000, … • The sequence repeats…. Registers and Counters

22. Synchronous Binary Counter • Design the counter • By inspection of the counting sequence • By a systematic procedure • State table • Karnaugh maps Registers and Counters

23. Synchronous Binary Counter Registers and Counters

24. Karnaugh Maps for Binary Counter Registers and Counters

25. Binary Counter with D Flip-Flops Registers and Counters

26. Karnaugh Maps for D Flip-Flops Registers and Counters

27. D Input Equations • DA = A+ = A’ • DB = B+ = BA’ + BA’ = B  A • DC = C+ = C’BA + CB’ + CA’ = C’BA + C(BA)’ = C  BA Registers and Counters

28. An Up-Down Binary Counter • U = 1, D = 0 • The counter counts up. • U = 0, D = 1 • The counter counts down. • U = 0, D = 0 • The counter state does not change. • U = 1, D = 1 • Not allowed. Registers and Counters

29. An Up-Down Binary Counter Registers and Counters

30. An Up-Down Binary Counter Registers and Counters

31. Binary Up-Down Counter Registers and Counters

32. A Loadable Counter • Two control signals • Ld (load) and Ct (count) • Ld = 1, Ct = 0 • Binary data is loadedinto the counter • Ld = 0, Ct = 1 • The counter is incremented • Ld = Ct = 0 • The counter holds its present value. • Ld = Ct = 1 • Load overrides count Registers and Counters

33. Counter Operation Registers and Counters

34. Implementation Registers and Counters