Unit 12 Registers and Counters

1. Unit 12Registers and Counters Ku-Yaw Chang canseco@mail.dyu.edu.tw Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

2. Outline 12.1 Registers and Register Transfers 12.2 Shift Registers 12.3 Design of Binary Counters 12.4 Counters for Other Sequences 12.5 Counter Design Using S-R and J-K Flip-Flops 12.6 Derivation of Flip-Flop Input Equations -- Summary Registers and Counters

3. Registers • Several D flip-flops may be grouped together with a common clock. • Each flip-flop can store one bit of information. • The following register store four bits of information Registers and Counters

4. Registers • Asynchronous clear inputs • A common clear signal – ClrN, requiring a logic 0 to clear flip-flops • Gating the clock can cause timing problems Registers and Counters

5. Registers • Flip-flops with clock enable are available • Load = 0 : the clock is disabled, and the register holds its data • Load = 1 : the clock is enabled, and the data applied to the D inputs will be loaded into the flip-flops (after the falling edge) Registers and Counters

6. Registers • 4-bit register using bus notation Registers and Counters

7. Data Transfer Between Registers Registers and Counters

8. Logic Diagram for 8-Bit Register Registers and Counters

9. Data Transfer Usinga Tri-State Bus Registers and Counters

10. Parallel Adder with Accumulator Registers and Counters

11. Adder Cell with Multiplexer Registers and Counters