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4.VHDL/Verilog Hierarchical Description

4.VHDL/Verilog Hierarchical Description. Hierarchical Connections: What port directions can be connected?. Case Study: Upper level to lower level or vice versa Input to input: ALLOWED Input to output or output to input: NOT ALLOWED

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4.VHDL/Verilog Hierarchical Description

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  1. 4.VHDL/Verilog Hierarchical Description

  2. Hierarchical Connections: What port directions can be connected? • Case Study: Upper level to lower level or vice versa • Input to input: ALLOWED • Input to output or output to input: • NOT ALLOWED • Input is already driven fromoutside. Don’t try to drive it from inside! • Output to output: ALLOWED • The output has to be driven from inside • Bidirectional: Only to Bidirectional Top_module Module1 Din Din Dout 8 A 8 8 EN B EN CLK A Module2 Data Din Data 8 8 8 C EN CLK CLK

  3. Hierarchical Connections: What port directions can be connected? • Case Study: At the same level • Input to input: • Allowed, but the connecting signal has to be driven! i.e. also connected to a source (output) • Input to output or output to input: • ALLOWED • Output to output: Not ALLOWED • Do not try to drive a signal by two different circuits! • Bidirectional: Only to Bidirectional Top_module Module1 Din Din Dout 8 A 8 8 EN B EN CLK A Module2 Data Din Data 8 8 8 C EN CLK CLK

  4. Hierarchical Connections: Code example SSG Decoder: module Ssg_decoder #( parameter CLK_FREQ = 50000000, parameter REFRESH_RATE = 1000 ) ( input CLK, input RESET, input [15:0] DIN, output [3:0] AN, output [6:0] SSG ); //We have to define the internal signals wire CE; wire [3:0] AN_Int; wire [1:0] mux_addr; wire [3:0] mux_data; #(CLK_FREQ, REFRESH_RATE) #(CLK_FREQREFRESH_RATE) Ssg_decoder Ssg_decoder Freq_divider CLK CLK #(CLK_FREQ, DIV_RATE) CLK CE_div CE CE Shift_reg_walk_0 AN CLK AN RESET RESET AN RESET 4 4 4 AN_Int CE AN_Int Priority_decoder Din Dout 2 4 mux_addr mux_addr Din[3:0] 2 Mux_4X_4To1 I0 4 [7:4] Din Din mux_data I1 mux_data O Hex_to_ssg_encoder 4 SSG I2 16 16 4 SSG 4 [11:8] Din Dout A I3 7 7 4 [15:11] 7 4

  5. Hierarchical Connections: Code example SSG Decoder: //connect now the internal modules //each module connection can be taken //from its definition: #(CLK_FREQREFRESH_RATE) #(CLK_FREQREFRESH_RATE) Ssg_decoder Ssg_decoder Freq_divider CLK CLK #(CLK_FREQ, DIV_RATE) CLK CE_div CE module #( parameter parameter ) ( input output ); #( ) ( ); . . . . Freq_divider CLK_FREQ DIV_RATE CLK, CE_div CE Shift_reg_walk_0 AN CLK AN = 50000000, = 50000 RESET RESET AN RESET 4 4 4 AN_Int CE AN_Int Priority_decoder Din Dout 2 4 mux_addr mux_addr Din[3:0] 2 Mux_4X_4To1 I0 4 [7:4] Din Din mux_data I1 mux_data O Hex_to_ssg_encoder 4 SSG I2 16 16 4 SSG 4 [11:8] Din Dout A I3 7 7 4 [15:11] 7 4

  6. Hierarchical Connections: Code example SSG Decoder: //connect now the internal modules //each module connection can be taken //from its definition: #(CLK_FREQREFRESH_RATE) #(CLK_FREQREFRESH_RATE) #(CLK_FREQREFRESH_RATE) Ssg_decoder Ssg_decoder Freq_divider CLK CLK #(CLK_FREQ, DIV_RATE) #(CLK_FREQ, DIV_RATE) CLK CE_div CE CE (CLK_FREQ), (REFRESH_RATE) My_Freq_divider_inst (CLK), (CE) Freq_divider #( . CLK_FREQ . DIV_RATE ) ( . CLK . CE_div ); Shift_reg_walk_0 AN CLK AN RESET RESET AN RESET 4 4 4 AN_Int CE AN_Int Priority_decoder Din Dout 2 4 mux_addr mux_addr Din[3:0] 2 Mux_4X_4To1 I0 • Remember: If the module has parameters to override, the instance name comes AFTER the parameter connections! • Check for the commas in the parameter and port list! 4 [7:4] Din Din mux_data I1 mux_data O Hex_to_ssg_encoder 4 SSG I2 16 16 4 SSG 4 [11:8] Din Dout A I3 7 7 4 [15:11] 7 4

  7. Hierarchical Connections: Code example SSG Decoder: #(CLK_FREQREFRESH_RATE) #(CLK_FREQREFRESH_RATE) #(CLK_FREQREFRESH_RATE) Ssg_decoder Ssg_decoder Freq_divider #( . CLK_FREQ (CLK_FREQ), . DIV_RATE (REFRESH_RATE) ) My_Freq_divider_inst ( . CLK (CLK) . CE_div (CE) ); //OR, keeping the order of parameters and //ports, the shortened version does not have //to contain the formal (internal) //parameters and ports: Freq_divider #(CLK_FREQ, REFRESH_RATE) My_Freq_divider_inst (CLK, CE); Freq_divider CLK CLK #(CLK_FREQ, DIV_RATE) #(CLK_FREQ, DIV_RATE) CLK CE_div CE CE Shift_reg_walk_0 AN CLK AN RESET RESET AN RESET 4 4 4 AN_Int CE AN_Int Priority_decoder Din Dout 2 4 mux_addr mux_addr Din[3:0] 2 Mux_4X_4To1 I0 4 [7:4] Din Din mux_data I1 mux_data O Hex_to_ssg_encoder 4 SSG I2 16 16 4 SSG 4 //NOT RECOMMENDED FOR//LARGE COMPONENTS: REDUCES//CODE VISIBILITY DRASTICALLY [11:8] Din Dout A I3 7 7 4 [15:11] 7 4

  8. Hierarchical Connections: Code example SSG Decoder: //In a similar manner: Shift_reg_walk_0 My_shift_reg_inst (.CLK (CLK), .RESET (RESET), .CE (CE), .AN (AN_Int) ); Priority_decoder My_decoder (.Din (AN_Int), .Dout (mux_addr)); Mux_4X_To1 My_mux_inst (.I0 (Din[3:0]), .I1 (Din[7:4]), .I2 (Din[11:8]) .I3 (Din[15:11]), .A (mux_data), .O (mux_addr) ); Hex_to_ssg_encoder My_encoder_inst (.Din (mux_data), .Dout (SSG) ); endmodule SSG Decoder: //In a similar manner: Shift_reg_walk_0 My_shift_reg_inst (.CLK (CLK), .RESET (RESET), .CE (CE), .AN (AN_Int) ); Priority_decoder My_decoder (.Din (AN_Int), .Dout (mux_addr)); Mux_4X_To1 My_mux_inst (.I0 (Din[3:0]), .I1 (Din[7:4]), .I2 (Din[11:8]), .I3 (Din[15:11]), .A (mux_data), .O (mux_addr) ); Hex_to_ssg_encoder My_encoder_inst (.Din (mux_data), .Dout (SSG) ); endmodule #(CLK_FREQREFRESH_RATE) #(CLK_FREQREFRESH_RATE) #(CLK_FREQREFRESH_RATE) Ssg_decoder Ssg_decoder Freq_divider CLK CLK #(CLK_FREQ, DIV_RATE) #(CLK_FREQ, DIV_RATE) CLK CE_div CE CE Shift_reg_walk_0 AN CLK AN RESET RESET AN RESET 4 4 4 AN_Int CE AN_Int Priority_decoder There are at least two errors in the code! Where? Din Dout 2 4 mux_addr mux_addr Din[3:0] 2 Mux_4X_4To1 I0 4 [7:4] Din Din mux_data I1 mux_data O Hex_to_ssg_encoder 4 SSG I2 16 16 4 SSG 4 [11:8] Din Dout A I3 7 7 4 [15:11] 7 4

  9. Hierarchical Connections: Code example SSG Decoder: //Corrected version: Shift_reg_walk_0 My_shift_reg_inst (.CLK (CLK), .RESET (RESET), .CE (CE), .AN (AN_Int) ); Priority_decoder My_decoder (.Din (AN_Int), .Dout (mux_addr)); Mux_4X_To1 My_mux_inst (.I0 (Din[3:0]), .I1 (Din[7:4]), .I2 (Din[11:8]), .I3 (Din[15:11]), .A (mux_addr), .O (mux_data) ); Hex_to_ssg_encoder My_encoder_inst (.Din (mux_data), .Dout (SSG) ); endmodule #(CLK_FREQREFRESH_RATE) #(CLK_FREQREFRESH_RATE) #(CLK_FREQREFRESH_RATE) Ssg_decoder Ssg_decoder Freq_divider CLK CLK #(CLK_FREQ, DIV_RATE) #(CLK_FREQ, DIV_RATE) CLK CE_div CE CE Shift_reg_walk_0 AN CLK AN RESET RESET AN RESET 4 4 4 AN_Int CE AN_Int Priority_decoder Din Dout 2 4 mux_addr mux_addr Din[3:0] 2 Mux_4X_4To1 I0 4 [7:4] Din Din mux_data I1 mux_data O Hex_to_ssg_encoder 4 SSG I2 16 16 4 SSG 4 [11:8] Din Dout A I3 7 7 4 [15:11] 7 4

  10. Hierarchical Connections Example in VHDL SSG Decoder: architecture my_arch of ssg_decoder is --internal signals signal CE: std_logic; signal AN_Int: std_logic_vector (3 downto 0); signal mux_addr: std_logic_vector (1 downto 0); signal mux_data: std_logic_vector (3 downto 0); --we have to declare each component --if not included in library component Freq_divider generic ( CLK_FREQ: integer := 50000000; DIV_RATE : integer := 1000 ); port (CLK : instd_logic; CE_div: outstd_logic ) endcomponent; … begin #(CLK_FREQREFRESH_RATE) #(CLK_FREQREFRESH_RATE) #(CLK_FREQREFRESH_RATE) Ssg_decoder Ssg_decoder Freq_divider CLK CLK #(CLK_FREQ, DIV_RATE) #(CLK_FREQ, DIV_RATE) CLK CE_div CE CE Shift_reg_walk_0 AN CLK AN RESET RESET AN RESET 4 4 4 AN_Int CE AN_Int Priority_decoder Din Dout 2 4 mux_addr mux_addr Din[3:0] 2 Mux_4X_4To1 I0 For component declaration the semicolon is present Every signal and component declaration is done between the architecture… begin statements 4 [7:4] Din Din mux_data I1 mux_data O Hex_to_ssg_encoder 4 SSG I2 16 16 4 SSG 4 [11:8] Din Dout A I3 7 7 4 [15:11] 7 4

  11. Hierarchical Connections Example in VHDL SSG Decoder: … begin My_Freq_divider_inst: Freq_divider genericmap ( CLK_FREQ => CLK_FREQ, DIV_RATE => REFRESH_RATE ) portmap ( CLK => CLK, CE_div => CE ); -- other instantiations -- and statements … endarchitecture my_arch; #(CLK_FREQREFRESH_RATE) #(CLK_FREQREFRESH_RATE) #(CLK_FREQREFRESH_RATE) Ssg_decoder Ssg_decoder Freq_divider CLK CLK #(CLK_FREQ, DIV_RATE) #(CLK_FREQ, DIV_RATE) CLK CE_div CE CE Shift_reg_walk_0 AN CLK AN RESET RESET AN RESET 4 4 Component instantiations and statements are done between the begin… endarchitecture statements For component instantiation the semicolon is not present Generic map and port map statements are followed by a list of ports, separated by commas 4 AN_Int CE AN_Int Priority_decoder Din Dout 2 4 mux_addr mux_addr Din[3:0] 2 Mux_4X_4To1 I0 4 [7:4] Din Din mux_data I1 mux_data O Hex_to_ssg_encoder 4 SSG I2 16 16 4 SSG 4 [11:8] Din Dout A I3 7 7 4 [15:11] 7 4

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