Research on Analysis and Physical Synthesis

1. Research on Analysis and Physical Synthesis Chung-Kuan Cheng CSE Department UC San Diego kuan@cs.ucsd.edu

2. Outlines • Analysis (Signal Integrity) • SPICEDiego • RLC Reduction • Synthesis (Interconnect Dominant) • Networks on Chip • Clock Distribution • Floorplanning • Datapath • Packaging (High Performance)

3. Analysis: SPICE • Large netlist, e.g. 100M transistors, 5G Hz • Strong Coupling: interconnect delay, crosstalk, voltage drop, ground bounce • Process Variations • Short Channel Devices

4. Why SPICEDiego is better? • SPICEDiego: fast accurate transistor level circuit simulator • Powerful Matrix Solver Engine • Transistor devices. • Capable of capturing coupling effects. • Device Model including Miller’s effect • Less Memory Requirement (no LU factorization, dose not save matrix for transistors) • Application • interconnect delay • Crosstalk • voltage drop, ground bounce • simultaneous switching noise

5. Experimental Results • Test Case • Board / Packaging / Chip Power Network • Fully coupled packaging inductance • 60k elements, 5000 nodes. • Spice failed • Our tool • Less than 10 minutes chip board Power Supply

6. Synthesis: Clock Distribution • Process variations causes significant amount of clock skew • Working frequency keeps increasing, skew accounts for large portion of clock period • Mesh is effective to reduce skew • There is no theoretical design guide line for mesh structure

7. State-of-the-art • In Engineering practice, very deep balanced buffer tree + mesh is widely adopted for global clock distribution • IBM Power 4: 64 by 64 grid at the bottom of an H-tree • Intel IA: clock stripe at the bottom of a buffer tree. • “Skew Averaging”: shunt at different levels • “Skew Averaging Factor” determined by simulation. No guideline for routing resource planning known yet

8. Clock Mesh Example (1) • DEC Alpha 21264

9. Clock Mesh Example (2) • IBM Power4 • H-tree drives one domain clock mesh • 8x8 area buffers

10. Clock Mesh Example (3) • Intel Pentium 4 • Tree drives three spines

11. Our Contributions and On-going Efforts Contribution: • Analytical skew expression using R,C model • Proposed generalized multi-level mesh network structure for skew reduction • Optimal allocation of routing resources among meshes On-going Study: • More accurate R,L,C delay model • Signal propagation on a uniform mesh

12. Multi-level mesh structure

13. Skew on mesh • Skew expression

14. Optimization • Skew function • Multi level skew function

15. GND + - GND Clock Design Settings • Die size 1cm by 1cm • 100nm copper technology • Ground Shielded Differential Signal Wires for Global Clock Distribution • Routing area is normalized to the area of a 16 by 16 mesh with minimal wire width

16. Delay Surfaces

17. Robustness Against Supply Voltage Variations

18. Packaging • Y Architecture • Chip-Package Breakaway

19. Grids of X and Y Architectures Y-Architecture X-Architecture (http://www.xinitiative.org/img/062102forum.pdf)

20. Clock Tree on Square Mesh • N-level clock tree: • path length 21% less than H-tree • total wire length 9% less than H tree, 3% less than X tree • No self-overlapping between parallel wire segments

21. Chip to Package Breakaway Manhattan Architecture

22. Y Architecture

23. Chip-Package Breakaways Indent Two sides Row by row Comparison

24. Conclusion • Analysis: Signal Integrity • Synthesis: Interconnect Dominant • Packaging: Performance Goals: Performance, Cost Resources: Physical Space Constraints: Yield, Signal Integrity