SYEN 3330 Digital Systems

SYEN 3330 Digital Systems Chapter 7 – Part 2 SYEN 3330 Digital Systems

Counters SYEN 3330 Digital Systems

Counter Basics: Divide by 2 SYEN 3330 Digital Systems

Divide Clock Frequency by 2 SYEN 3330 Digital Systems

Ripple Counter SYEN 3330 Digital Systems

Ripple Counter (Continued) SYEN 3330 Digital Systems

Synchronous Counters SYEN 3330 Digital Systems

Synchronous Counters (Continued) SYEN 3330 Digital Systems

Synchronous Counters – Serial Gating • When a two-input AND gate is used for each stage of the counter with a “ripple-like” carry, this is referred to as serial gating. • As the size of the counter increases the delay through the combinational logic increases roughly in proportion to n, the number of stages. SYEN 3330 Digital Systems

Synchronous Counters – Parallel Gating • When a multiple-input ( >2) AND gates are used for each stage of the counter with logic dedicated to each stage or to a group of stages, this is referred to as parallel gating. It resembles carry lookahead in an adder. • As the size of the counter increases the delay through the combinational logic increases roughly in proportion to n/m, the number of stages/the group size. SYEN 3330 Digital Systems

Design: Synchronous BCD SYEN 3330 Digital Systems

Q2 Q2 T8 T4 1 0 1 3 2 0 1 3 2 1 1 Q4 Q4 4 5 7 6 4 5 7 6 x x x x x x x x 12 13 15 14 12 13 15 14 Q8 Q8 x x x x 1 8 9 11 10 8 9 11 10 Q1 Q1 Q2 Q2 T2 T1 1 1 1 1 1 1 0 1 3 2 0 1 3 2 1 1 1 1 1 1 Q4 Q4 4 5 7 6 4 5 7 6 x x x x x x x x 12 13 15 14 12 13 15 14 Q8 Q8 x x x x 1 1 8 9 11 10 8 9 11 10 Q1 Q1 Synchronous BCD (Continued) • Use K-Maps to minimize the next state function: SYEN 3330 Digital Systems

"1" Q1 Q T CP Q Q2 Q T Q8*Q1 Q Q T Q4 Q2*Q1 Q Q4*Q2*Q1 Q8 T Q Q8*Q1 Q Synchronous BCD (Continued) • The minimized circuit: SYEN 3330 Digital Systems

Synchronous BCD (Continued) SYEN 3330 Digital Systems

Counter with Parallel Load SYEN 3330 Digital Systems

Counting Modulo N SYEN 3330 Digital Systems

"0" Q8 IN8 "0" Q4 IN4 "0" Q2 IN2 "0" Q1 IN1 CP CLOCK LOAD "1" CLEAR Counting Modulo 7 SYEN 3330 Digital Systems

"1" Q8 IN8 "0" Q4 IN4 "0" Q2 IN2 "1" Q1 IN1 CP CLOCK LOAD "1" CLEAR Counting Modulo 7, Preset 9 SYEN 3330 Digital Systems

Timing Sequences SYEN 3330 Digital Systems

"1" C3 Ripple Counter C2 Q2 C1 Q2 Q1 CP CP C0 Q1 CP C3 C2 C1 "GLITCH" C0 Counter Decoder Example SYEN 3330 Digital Systems

Ring Counter SYEN 3330 Digital Systems

Johnson Counter (Switch-Tail) BC SYEN 3330 Digital Systems

Verilog for Registers and Counters • Register – same as flip-flop except multiple bits:reg[3:0] Q; input[3:0] D; always@(posedge CLK orposedge RESET) begin if (RESET) Q <= 4'b0000; else Q <= D; end • Shift Register – use concatenate: Q <= {Q[2:0], SI}; • Counter – use increment/decrement: count <= count + 1; or count <= count - 1 SYEN 3330 Digital Systems

Verilog Description of Left Shift Register // 4-bit Shift Register with Reset // (See Figure 5-3) module srg_4_r_v (CLK, RESET, SI, Q,SO); input CLK, RESET, SI; output [3:0] Q; output SO; reg [3:0] Q; assign SO = Q[3]; always@(posedge CLK or posedge RESET) begin if (RESET) Q <= 4'b0000; else Q <= {Q[2:0], SI}; end endmodule SYEN 3330 Digital Systems

Verilog Description of Binary Counter // 4-bit Binary Counter with Reset // (See Figure 5-10) module count_4_r_v (CLK, RESET, EN, Q, CO); input CLK, RESET, EN; output [3:0] Q; output CO; reg [3:0] count; assign Q = count; assign CO = (count == 4'b1111 && EN == 1'b1) ? 1 : 0; always@(posedge CLK or posedge RESET) begin if (RESET) count <= 4'b0; else if (EN) count <= count + 1; end endmodule SYEN 3330 Digital Systems

SYEN 3330 Digital Systems