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SYEN 3330 Digital Systems

SYEN 3330 Digital Systems. Chapter 2 Part 7. NAND and NOR Implementation. NAND Gates. NAND Gates (Cont.). NAND Implementation. NAND Implementation (Cont.). Degenerate AND Term. NAND-NAND Example. NAND-NAND Example. NOR Gates. NOR Implementation. Useful Transformations.

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SYEN 3330 Digital Systems

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  1. SYEN 3330 Digital Systems Chapter 2 Part 7 SYEN 3330 Digital Systems

  2. NAND and NOR Implementation SYEN 3330 Digital Systems

  3. NAND Gates SYEN 3330 Digital Systems

  4. NAND Gates (Cont.) SYEN 3330 Digital Systems

  5. NAND Implementation SYEN 3330 Digital Systems

  6. NAND Implementation (Cont.) SYEN 3330 Digital Systems

  7. Degenerate AND Term SYEN 3330 Digital Systems

  8. NAND-NAND Example SYEN 3330 Digital Systems

  9. NAND-NAND Example SYEN 3330 Digital Systems

  10. NOR Gates SYEN 3330 Digital Systems

  11. NOR Implementation SYEN 3330 Digital Systems

  12. Useful Transformations SYEN 3330 Digital Systems

  13. Graphical Transformations SYEN 3330 Digital Systems

  14. General Two-level Implementations SYEN 3330 Digital Systems

  15. General Implementations (Cont.) SYEN 3330 Digital Systems

  16. Implementation Example SYEN 3330 Digital Systems

  17. Implement F in AND-NOR form Implement the network: SYEN 3330 Digital Systems

  18. Multi-level NAND Implementations • Add inverters in two-level implementation into the cost picture • Attempt to “combine” inverters to reduce the term count • Attempt to reduce literal + term count by factoring expression into POSOP or SOPOS SYEN 3330 Digital Systems

  19. Multi-level NAND Example 1 • F = A B’ + A C’ + B A’ + B C’ = A A’ + A B’ + A C’ + B A’ + B B’ + B C’ = A (A’ + B’ + C’) + B (A’ + B’ + C’) 15 inputs and 8 gates* 7 inputs and 4 gates A B F C * Counting inverters (NOTS) as 1 input and 1 gate SYEN 3330 Digital Systems

  20. Multilevel NAND Example 2 • F = AB + AD’ + BC + CD’12 inputs & 5 gates = A(B + D’) + C(B + D’)8 inputs & 5 gates A B F D C SYEN 3330 Digital Systems

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