Updates from Lab 4-120

1. Updates from Lab 4-120 Andrew Peck & ShayanRastegari May 01, 2014

2. U76 Bus Hold Chip • Discovered that one wrong chip was installed on OTMB baseboards.. U76 chip is responsible for keeping the JTAG signals at well-defined logic levels during FPGA initialization, until the JTAG state machine starts. • With wrong chip, a floating signal is driving a buffer, which would output some psuedorandom logic being send to a psuedorandom JTAG chain. • With correct chip, buffer outputs will stay at their previously held logic level until a driving signal changes them.. • Original problem with TMB2005 was discovered by Greg.. If a RAT was installed in the crate, TMBs would lock up when issued hard-reset. • Problems were never discovered in ME11. Some reasons: • RATs are without firmware, so they won’t have any response to JTAG instructions • ALCTs are all Spartan-6: long initialization time (129 ms).. Mezzanine would not respond to JTAG instructions… Slow control FPGA may still be problematic • Level shifters on the Optical mezzanine may be inadvertently performing a similar bus-hold function.. (unsure) • Some possible solutions: • Straightforward but painful: replace all of the U76 chips. May still have issues due to the level shifters? Depends on how the level shifters respond to floating inputs.. • Possible firmware fix: spurious data would likely be putting the JTAG controllers into bad states.. From any state, the JTAG controllers can be reset to a good “test-logic-reset” state with 5 clocks of test-mode-select. A JTAG test-logic-reset command could automatically be sent to all devices after hard-reset. May or may not fix the problem.. Jason is talking with Ben • Wondering why the TMB locking-up was never seen at UCLA..? Considering to reinstall one of the old chips back on a TMB to investigate.

3. ALCT JTAG Test Software • Started working on the software for the ALCT baseboard test.. • Tried to get existing code to compile… but some significant hurdles • Need old versions of some proprietary software.. Not for sale now.. Couldn’t find for download. Also discovering some major issues in the code. Don’t know how it ever compiled in the first place (e.g. some functions misspelled). Spoke with an engineer at Embaradero.. He had no recommendations for any simple way to get the existing code working (he suggested rewriting large portions entire existing code with different graphical widgets and porting to free Pascal ) • Started a total rewrite of the code (in Python) to see how feasible it would be… turned out to be easier than expected. Managed to get working: • LPT driver • JTAG controller • Mostly all of the ALCT backend functions have been tested.. e.g. read/write thresholds, voltages, ID codes, standby registers, etc.. • Complete “slow control self test” • Thresholds linearity test • Haven’t done: • Tester boards test • Delays pattern test • Some kind of interface..

4. Updated Tables in TMB Documentation • Xiaofeng discovered a table in the TMB specifications with bad/outdated pin assignments on the RPC backplane connectors. • Some other tables turned out to be incorrect as well.. Was unchanged from TMB2004 assignments and backplane connectors. • Now corrected in the latest TMB documentation. • Moved Peter out of the basement ! • Lab has moved! Peter is now upstairs with us.

5. Next… • Make some additions to the csc-fw repository (https://github.com/csc-fw) • Added files to local clone of the repository.. Need to talk to Manuel and submit pull request. • Continue to look at the U76 issue.. Probably install the old chip on one of our TMBs, see if I can reproduce the problem. • Finish some more work on the ALCT test software.. Almost in a state that it could replace the existing software. • Work with Jason to include something about the U76 issue in the TMB documentation.. The change of chip was previously not documented (schematics + docs all had the old chip specified).