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AT17 Series EEPROM Configuration Memories

AT17 Series EEPROM Configuration Memories. Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Hotline (408) 436-4119 fpga@atmel.com OR configurator@atmel.com. architecture behave of CNT6 is signal SQA, SQB : integer range 0 to 6 := 1; begin QA <= To_Vector(3,SQA);.

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AT17 Series EEPROM Configuration Memories

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  1. AT17 Series EEPROM Configuration Memories Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 Hotline (408) 436-4119 fpga@atmel.com OR configurator@atmel.com

  2. architecture behave of CNT6 is signal SQA, SQB : integer range 0 to 6 := 1; begin QA <= To_Vector(3,SQA); Tpd = 10 ns Fmax = 100 MHz Size = 12x8 Cells Icc = .2mA/MHz 10100010 01101001 11101011 Configurator Download Board Layout Behavioral VHDL/Verilog Synthesis Macro Generators Program Configuration Memory Place & Route ATDH2200 ATDH2225 Third Party Programmer Schematic Timing Analysis Design Entry & Simulation Physical Design (Including synthesis compiler) Libraries & Interface

  3. SRAM-Based FPGA/FPSLIC - Atmel - Altera - Lucent - Xilinx Configurator FPGA/FPSLIC ISP Configuration Memories65K, 128K, 256K, 512K, 1M, 2M & 4M Serial EEPROMs(Direct Xilinx & Altera OTP Replacement) • 7 Sizes • AT17C65 - 65K Version (8/20 pins) • AT17C128 - 128K Version (8/20 pins) • AT17C256 - 256K Version (8/20 pins) • AT17C512 - 512K Version (8/20 pins) • AT17C010 - 1Meg Version (8/20 pins) • AT17C020 - 2Meg Version (20 pins) • AT17C040 - 4Meg Version (44 pins) Q3/2001 • Interface with any Atmel or other SRAM FPGA & FPSLIC • - AT6000/AT40K (Atmel FPGA) - OR2/3/4Cxx (ORCA) • - AT94K (Atmel FPSLIC) - Altera 1K/6K/8K/10K/20K (Flex) • - XC2000/3000/4000/5200 - Spartan XCS • - Xilinx Vertex XCV - Cypress Delta39K • Up to 15 MHz configuration rate • Fast, ISP via 2-wire interface • 3V (17LV) & 5V (17C) options RECONFIGURABLE! Were #1 in Prog. Logic ISP memories

  4. ISP 5V or 3.3V Fast programming up to 15MHz Cascade– Multiple devices can be cascaded. Reconfigurable FPGA Memory EEPROM is priced competitively with OTP products Two Parts in One AT17Cxxx can also emulate 24Cxxx parts In System (Re)Programmable Easy system hook-up for ISP operation Can be soldered to PCB - no socket required Key Features and Benefits

  5. Use ‘spare’ memory like a 24Cxxx device. Save on cost/Board space/Power consumption. Use ISP interface mux to enable 2-wire SEEPROM capability. Two Parts in One 0000 FPGA Configuration memory requirements are stored from zero page to 1AD7 Hex. This memory space is accessed in AT17Cxxx mode by the FPGA (SerEn =1) 17CXXX 1AD7 ‘Unused’ memory at the end of the AT17Cxxx can be accessed in 24Cxxx mode (SerEn=0). Information such as last number redial/PCI I.D. Plug and Play/IP address etc. can easily be stored or retrieved using a micro-controller. 1B00 24CXXX 1FFF AT17 Device Address space.

  6. New Parts / Old Parts Design Differences OSC : Internal Oscillator function available WP : Write Protect, this feature allows portions of the memory to be blocked during Write instructions.

  7. Configurator Availability Atmel & Xilinx Versions • AT17C/F series = 2-wire serial ISP • AT18F series = JTAG ISP

  8. Configurator Availability Altera Versions • AT17C/F series = 2-wire serial ISP • AT18F series = JTAG ISP

  9. ISP Programming Use Mux for ISP circuit Simple ISP circuit Figure 2: In-System Programming of AT17C/LV65/128/256 (new) EEPROM in AT40K FPGA Application Figure 1: In-System Programming of AT17C/LV65/128/256 (old) EEPROM in AT40K FPGA Application

  10. AT17(A) Internal oscillator is enabled by default 'A' part is recommended for Altera users Pin out is different Oscillator must be enabled for Altera’s Flex 1K,10K & 6K family, disabled for Altera’s Flex 8K family ‘A’ Vs ‘Non A’ EEPROMHigh Density EEPROM AT17(Non A) Internal oscillator is disabled by default • Non-A part is recommended for Atmel, Xilinx, and Lucent users

  11. ATDH2200 board for ISP and stand-alone device programming ATDH2225 for ISP - Recommended for Atmel custom board layout - Allows cascading controlled by software Broad third party programmer support Faster to program than OTP parts Source Code is available - For development of Microcontrolled programming Programming Options

  12. PC Programmer kit for ALL AT17 Series EEPROMs Standalone programming of Configuration EEPROM, OR Interface to target board for In-System Programming Supports .pof, .rbf, .hex, .mcs and .bst file formats Takes files straight from Atmel/Xilinx/Altera/Lucent software 5V and 3.3V operation (from supply or target board) Choice of 20pin PLCC or SOIC socket adapter ATDH2221 for all 20 pin SOIC ATDH2222 for all 20 pin PLCC (incl. Altera, 2M) • ATDH2223 for all 8 pin SOIC • ATDH2224 for 44 pin TQFP • ATDH2226 for 32 pin TQFP • ATDH2227 for 44 pin PLCC Directly supported by Atmel’s IDS FPGA software CPS (Configurator Programming System) software Quick start user’s guide NEW! NEW! NEW! ATDH2200E

  13. ATDH2200 Stand-alone Device Programming Parallel Cable DB-25M ATDH2200 Parallel Port DB-25F PC AT17CXXX Configurator Socket

  14. ATDH2200 In-System Programming Parallel Cable 10-pin Ribbon Cable Target System DB-25M ATDH2200 Parallel Port FPGA FPGA DB-25F PC In-System Programming Connector Header In-System Programming Connector Header AT17CXXX Configurator

  15. NEW! ATDH2225 In-System Programming Cable Target System DB-25M ATDH2225 Parallel Port FPGA FPGA PC Programming Dongel In-System Programming Connector Header AT17CXXX Configurator

  16. CPS Configurator Programming Software • AT17 Configurator Programming System s/w • Clear and compact GUI • Windows 95/98/NT/2000 support • 2Meg device support • Partitions Altera bitstream files for use in third party programmers • Reset polarity verification (on ATDH2200E only) • Download data rate calibrated to PC processor • Save and restore settings between sessions • Enable/Disable internal clock for Altera ‘A’ parts • Online help and link to WWW-based FAQ

  17. Program from Atmel .bst file format [AT40K] CF /P /I input_file.bst /S code /Z level [/G] [/D LPT1] Program from Altera .pof or .hex file formats CF /A /I input_file.pof /S code /Z level [/D LPT1] CF /A /I input_file.hex /S code /Z level [/D LPT1] Program from Xilinx .mcs file format CF /E /I input_file.mcs /S code /Z level [/D LPT1] Density ‘codes’ are 65, 128, 256, 512, 010 2Meg part supported in CPS (GUI version of CF) only Reset ‘levels’ are L (active low) or H (active high) Altera file conversion for 3rd party programmers CF /B /I input_file.pof /O output_file.bst /F HEX CF /B /I input_file.hex /O output_file.bst /F HEX Source code for CF available on request (cf.c) CF.EXE(Windows 3.1/95/98 DOS software)

  18. Configurator AT40K Configuration Statistics Device Configuration Bits* Configurator AT40K05 63K AT17C/LV65 AT40K10 135K AT17C/LV256 AT40K20 236K AT17C/LV256 AT40K40 521K AT17C/LV512 AT40K80 916K AT17C/LV010 AT40K125 1419K AT17C/LV020 AT40K * = Can be reduced by using bit-stream compression option

  19. Configurator FPSLIC Configuration Statistics Device Configuration Bits* Configurator* AT94K10 423K AT17LV512 AT94K20 524K AT17LV010 AT94K40 809K AT17LV010 AT94K * = Can be reduced by using bit-stream compression option

  20. Drop-In of AT17C65/128/256 AT40K FPGA Application

  21. ISP of AT17C/LV65/128/256(Old Vs New) EEPROM Old (using Multiplexor) New (No Multiplexor)

  22. Drop-In of AT17C512/010/002 AT40K FPGA Application

  23. In-System Programming of the AT17C/LV512/010/002 AT40K FPGA Application

  24. ISP of New Low Density(AT17C/LV65/128/256) VS High Density(AT17C/LV512/010/002)

  25. Drop-In of AT17C65/128/256 AT60xx FPGA Application

  26. In-System Programming of the AT17C65/128/256 (Old) RESET/OE Programming Arrangement AT60xx FPGA Application Old Version

  27. In-System Programming of the AT17C65/128/256 (New) RESET/OE Programming Arrangement AT60xx FPGA Application New Version Note : Reset Polarity of the EEPROM is programmed HIGH for AT6K devices

  28. Drop-In Replacement of XC17/AT17 PROMs Xilinx/Lucent FPGA Application

  29. In-System Programming of the AT17C65/128/256 RESET/OE Programming Arrangement Xilinx/Lucent FPGA Application

  30. In-System Programming of the AT17C512/010/002 Xilinx/Lucent FPGA Application

  31. In-System Programming of the AT17C512/010/002 Cascaded Arrangement Xilinx/Lucent FPGA Application

  32. In-System Programming of the AT17C/LV020 Xilinx/Lucent FPGA Application

  33. Drop-In Replacement of the EPC1064/EPC1213 External Oscillator Arrangement Altera FPGA Application

  34. In-System Programming of Old Low Density(AT17C/LV65A/128A/256A) VS New Low Density(AT17C/LV65A/128A/256A) using Altera FPGA Old (using Multiplexor) New (No Multiplexor)

  35. Drop-In Replacement of the EPC1064/EPC1213 Altera FPGA Application

  36. Drop-In Replacement of the EPC1441/EPC1/EPC2 Internal Oscillator Arrangement Altera FPGA Application

  37. Drop-In Replacement of the EPC1441/EPC1/EPC2 Internal Oscillator and Cascaded Arrangemen Altera FPGA Application

  38. In-System Programming of the AT17C65(A)/128(A)/256(A) RESET/OE Programming Arrangement Altera FPGA Application

  39. In-System Programming of the AT17C65A/128A/256A(older version) RESET/OE Programming with External Oscillator Arrangement Altera FPGA Application

  40. In-System Programming of the AT17C512A/010A/002A Altera FPGA Application

  41. In-System Programming of the AT17C512A/010/002A Internal Oscillator Arrangement Altera FPGA Application

  42. In-System Programming of the AT17C512A/010A/002A Internal Oscillator and Cascaded Arrangement Altera FPGA Application

  43. In-System Programming of the AT17C512A/010A/002A External Oscillator Arrangement Altera FPGA Application

  44. In-System Programming of the AT17C/LV020A Internal Oscillator Arrangement Altera FPGA Application

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