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Virtual Memory Sample Questions Project 3 – Build Pthread Lib Extra Office Hour: Wed 4pm-5pm HILL 367. Recitation 6. Memory Hierarchy. Virtual Memory. Answer: Pretend we had something bigger => Virtual Memory. Memory. Cache. Registers. Memory Access Cost.
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Virtual MemorySample QuestionsProject 3 – Build Pthread LibExtra Office Hour: Wed 4pm-5pm HILL 367 Recitation 6
Memory Hierarchy Virtual Memory Answer: Pretend we had something bigger => Virtual Memory Memory Cache Registers
Virtual MemoryPaging (1) The position and function of the MMU
Paging (2) The relation betweenvirtual addressesand physical memory addres-ses given bypage table
Paging: Address Translation virtual address p d f CPU physical address d f d p f memory page table
Page Tables (1) Internal operation of MMU with 16 4 KB pages
Translation Lookaside Buffers • Translation on every memory access must be fast • What to do? Caching, of course … • Why does caching work? Temporal locality! • Same as normal memory cache – cache is smaller so can spend more $$ to make it faster • Cache for page table entries is called the Translation Lookaside Buffer (TLB) • Typically fully associative • Relatively small number of entries (e.g., 64 or 128 entries) • On every memory access, we look for the page frame mapping in the TLB
Paging: Address Translation with TLB TLB hit/ TLB miss virtual address p d f CPU physical address d f d TLB p/f memory f
Terms • Page frames • (Virtual) Pages • Page fault • Hit /Miss • Page table • TLB
Page Replacement • Highly motivated to find a good replacement policy • That is, when evicting a page, how do we choose the best victim in order to minimize the page fault rate? • Is there an optimal replacement algorithm? If yes, what is it? • Let’s look at an example: • Suppose we have 3 memory frames and are running a program that has the following reference pattern 7, 0, 1, 2, 0, 3, 0, 4, 2, 3 • Algorithms: Optimal, Not Recently Used(NRU), Second Chance, FIFO, LRU(Least Recently Used), Working Set & Clock, Nth Chance …
Optimal Page Replacement • Suppose we know the access pattern in advance 7, 0, 1, 2, 0, 3, 0, 4, 2, 3 • Optimal algorithm is to replace the page that will not be used for the longest period of time • What’s the problem with this algorithm? • Realistic policies try to predict future behavior on the basis of past behavior • Works because of locality
Not Recently Used Page Replacement Algorithm • Each page has Reference bit, Modified bit • bits are set when page is referenced, modified • Pages are classified • not referenced, not modified • not referenced, modified • referenced, not modified • referenced, modified • NRU removes page at random • from lowest numbered non empty class
FIFO Page Replacement Algorithm • Maintain a linked list of all pages • in order they came into memory • Page at beginning of list replaced (remove the last cell) • Disadvantage • Last cells may be often used
Least Recently Used (LRU) • Assume pages used recently will used again soon • throw out page that has been unused for longest time • Must keep a linked list of pages • most recently used at front, least at rear • update this list every memory reference !! • Alternatively keep counter in each page table entry • choose page with lowest value counter • periodically zero the counter
Segmentation (1) • One-dimensional address space with growing tables • One table may bump into another
Segmentation (2) Allows each table to grow or shrink, independently
Segmentation (3) Comparison of paging and segmentation
Implementation of Pure Segmentation (a)-(d) Development of checkerboarding (e) Removal of the checkerboarding by compaction
Segmentation with Paging: MULTICS (1) • Descriptor segment points to page tables • Segment descriptor – numbers are field lengths
Segmentation with Paging: MULTICS (2) A 34-bit MULTICS virtual address
Example Question1 • 4 page frames, page requests=0172327103 • Page Fault Rate??? For FIFO, LRU, (OPT) LRU MMMMMH H HMM 0 1 7 2 3 2 7 1 0 3 0 1 7 2 3 2 7 1 0 3 0 1 7 2 3 2 7 1 0 0 1 7 7 3 2 7 1 0 1 1 1 3 2 7 FIFO MMMMMH H HMH 0 1 7 2 3 2 7 1 0 3 0 1 7 2 3 3 3 3 0 0 0 1 7 2 2 2 2 3 3 0 1 7 7 7 7 2 2 0 1 1 1 1 7 7
Example Question 2 Assume a process is divided into 4 equal-sized segments, and that the system builds a 16-entry page descriptor for each segment. Thus, the system has a combination of segmentation & paging. Assume also that the page size is 4KB. • What is the maximum size of each segment? • Assume that an element in physical location 0x21ABC (in hex) is accessed by a thread of this process. What segment, page & offset is the thread trying to access? • ANSWER: • 16 * 4KB • 4K = 2^12, therefore, ABC is for offset. • 16=2^4, page 1. • and “2” is for segment
Example Question 3 A computer has 32-bit virtual addresses & 4-KB pages. The program and data together fit in the lowest page (0-4095). The stack fits in the highest page. How many entries are needed in the page table if one-level paging is used? How many for 2-level page, with 10 bits in each part? ANSWER: Twenty bits are used for the virtual page numbers, leaving 12 over for the offset. This yields a 4-KB page. Twenty bits for the virtual page implies 2^20 pages.
Example Question 4 A computer whose processes have 1024 pages in their address spaces keeps its page tables in memory. The overhead required for reading a word from the page table is 5 ns. To reduce this overhead, the computer has a TLB, which hold 32 (virtual page->physical page frame) pairs, and can do a look up in 1 ns. What hit rate is needed to reduce the mean overhead to 2 ns? ANSWER: The effective instruction time is 1h + 5(1 − h), where h is the hit rate. If we equate this formula with 2 and solve for h, we find that h must be at least 0.75.
Project 3 • Nov 7, 2008 5:00 pm • Implement basic functions of Pthread Lib. • Use makecontext(), getcontext(), setcontext(), and swapcontext(). • Useful Link: • http://www.opengroup.org/onlinepubs/009695399/functions/makecontext.html