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Implementation of a GNSS Space Receiver on a Zynq

Implementation of a GNSS Space Receiver on a Zynq. Marc Majoral, Javier Arribas CTTC SEFUW 2018 10-4-2018. Outline. About CTTC Zynq SoC GNSS Space Receiver on a Zynq The GNSS-SDR software HW Accelerators in the PL Implementation of the HW Accelerators

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Implementation of a GNSS Space Receiver on a Zynq

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  1. Implementation of a GNSS Space Receiver on a Zynq Marc Majoral, Javier Arribas CTTC SEFUW 2018 10-4-2018

  2. Outline • About CTTC • Zynq SoC • GNSS Space Receiver on a Zynq • The GNSS-SDR software • HW Accelerators in the PL • Implementation of the HW Accelerators • Implementation of the GNSS-SDR software in Zynq • System Validation

  3. About CTTC • Non-profit research institution based in Castelldefels (Barcelona) • Research focused on technologies related to the physical, data-link and network layers of communication systems. • Groups: • Communication systems division • Communication technologies division • Communication networks division • Geomatics division

  4. Xilinx Z7035 • PS: dual-core ARM Cortex-A9 clocked up to 800 MHz. • PL: Xilinx’s Kintex-7 FPGA with 275 k logic cells and 900 DSP48 slices.

  5. GNSS Space Receiver on a Zynq • GNSS Software Defined Space Receiver running on a consumer-based powerful SoC. • Move the computationally intensive parts of the GNSS receiver algorithms to the FPGA part of the SoC (high-speed correlation functions and digital filtering of base-band signals. • Test Board: ADRV9361-Z7035

  6. ADRV1CRR-BOB Carrier Board

  7. The GNSS-SDR gnss-sdr.org

  8. The GNSS-SDR • GNSS: Global Navigation Satellite Systems. The acronym that encompasses those systems that allow users to compute their position based on signals transmitted by satellites, world-wide. • SDR: Software Defined Receiver • Based on GNURadio • Runs on the ARMs

  9. The GNSS-SDR

  10. The GNSS-SDR

  11. The Hardware Accelerators in the FPGA

  12. The Hardware Accelerators in the FPGA

  13. The Hardware Accelerators in the FPGA

  14. The Hardware Accelerators in the FPGA

  15. Implementation of the HW Accelerators (Acquisition and Tracking Engines) • Development Tools: Xilinx Vivado • Programming Language: VHDL • Unit-tests running in the VHDL simulator • Packaged as re-usable IP-XACT cores (The Vivado Tools automatically perform that) • Main Project instantiates the HW Accelerators, other Xilinx IP cores and Analog Devices IP cores. • Interface between the ARMs and the HW Accelerators in the FPGA: AXI4 Bus. • Xilinx Vivado Tool automatically assigns Phy addresses to the IP cores

  16. Implementation of the GNSS-SDR software in Zynq • Linux Filesystem created and GNSS-SDR cross-compiled for ARM using the Yokto SDK in Linux. • Linux Kernel: Petalinux. • Petalinux compiler uses the Vivado compiled file to generate a Device Tree. • Some entries in the Device Tree may be manually introduced. • Linux Kernel image, Linux Filesystem and FPGA bitstream is copied to an SD card.

  17. Communication between GNSS-SDR and the HW Accelerators • UIO driver installed in Linux: maps HW accelerator AXI4 address space to user process address space. The user process address space can be accessed from the GNSS-SDR code.

  18. System Validation

  19. Future work • Limit the use of single core, allowing exploitation of the other core for other applications • Reduce power consumption • Make code compliant with the MISRA C++ coding standard • Increase the reliability of the system for space applications.

  20. Thanks for your kind attention! Questions? Marc Majoral, Javier Arribas CTTC SEFUW 2018 10-4-2018

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